mc68hc908mr32 Freescale Semiconductor, Inc, mc68hc908mr32 Datasheet - Page 67

• Manufacturer Part Number: mc68hc908mr32
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

PCTL[3:0] — Unimplemented Bits
4.5.2 PLL Bandwidth Control Register
The PLL bandwidth control register (PBWC):
AUTO — Automatic Bandwidth Control Bit
LOCK — Lock Indicator Bit
ACQ — Acquisition Mode Bit
Freescale Semiconductor
These bits provide no function and always read as logic 1s.
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This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual
operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit.
When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK,
is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as logic 0
and has no meaning. Reset clears the LOCK bit.
When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode
or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is
in acquisition or tracking mode.
In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is
stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
1 = Automatic bandwidth control
0 = Manual bandwidth control
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
1 = Tracking mode
0 = Acquisition mode
Selects automatic or manual (software-controlled) bandwidth control mode
Indicates when the PLL is locked
In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode
In manual operation, forces the PLL into acquisition or tracking mode
Address: $005D
if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and
BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0),
selecting CGMVCLK requires two writes to the PLL control register. See
4.3.3 Base Clock Selector
Reset:
Read:
Write:
AUTO
Bit 7
Figure 4-6. PLL Bandwidth Control Register (PBWC)
R
0
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
= Reserved
LOCK
R
6
0
ACQ
Circuit.
5
0
XLD
4
0
R
3
0
0
R
2
0
0
R
1
0
0
Bit 0
R
0
0
CGM Registers
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