ade7518 Analog Devices, Inc., ade7518 Datasheet - Page 95

• Manufacturer Part Number: ade7518
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc, And Lcd Driver
• Manufacturer: Analog Devices, Inc.

Table 95. Timer 0 High Byte SFR (TH0, 0x8C)
Bit
7 to 0
Table 96. Timer 0 Low Byte SFR (TL0, 0x8A)
Bit
7 to 0
Table 97. Timer 1 High Byte SFR (TH1, 0x8D)
Bit
7 to 0
Table 98. Timer 1 Low Byte SFR (TL1, 0x8B)
Bit
7 to 0
Table 99. Timer 2 High Byte SFR (TH2, 0xCD)
Bit
7 to 0
Table 100. Timer 2 Low Byte SFR (TL2, 0xCC)
Bit
7 to 0
Table 101. Timer 2 Reload/Capture High Byte SFR
(RCAP2H, 0xCB)
Bit
7 to 0
Table 102. Timer 2 Reload/Capture Low Byte SFR
(RCAP2L, 0xCA)
Bit
7 to 0
TIMER 0 AND TIMER 1
Timer/Counter 0 and Timer/Counter 1 Data Registers
Each timer consists of two 8-bit registers. They are Timer 0
High Byte SFR (TH0, 0x8C), Timer 0 Low Byte SFR (TL0, 0x8A),
Timer 1 High Byte SFR (TH1, 0x8D), and Timer 1 Low Byte SFR
(TL1, 0x8B). These can be used as independent registers or
combined into a single 16-bit register, depending on the timer
mode configuration (see Table 95 to Table 98).
Timer/Counter 0 and Timer/Counter 1 Operating Modes
This section describes the operating modes for Timer/Counter 0
and Timer/Counter 1. Unless otherwise noted, these modes of
operation are the same for both Timer 0 and Timer 1.
Mnemonic
TL2
Mnemonic
Mnemonic
Mnemonic
Mnemonic
Mnemonic
TH0
TL0
TH1
TL1
TH2
Mnemonic
TH2
Mnemonic
TL2
Default
0
Default
0
Default
0
Default
0
Default
0
Default
0
Default
0
Default
0
Description
Timer 0 Data High Byte.
Description
Timer 0 Data Low Byte.
Description
Timer 1 Data High Byte.
Description
Timer 1 Data Low Byte.
Description
Timer 2 Data High Byte.
Description
Timer 2 Reload/
Capture High Byte.
Description
Timer 2 Reload/
Capture Low Byte.
Description
Timer 2 Data Low Byte.
Rev. 0 | Page 95 of 128
Mode 0 (13-Bit Timer/Counter)
Mode 0 configures an 8-bit timer/counter. Figure 82 shows
Mode 0 operation. Note that the divide-by-12 prescaler is not
present on the single cycle core.
In this mode, the timer register is configured as a 13-bit register.
As the count rolls over from all 1s to all 0s, it sets the timer
overflow flag, TF0. TF0 can then be used to request an interrupt.
The counted input is enabled to the timer when TR0 = 1 and either
Gate0 = 0 or INT0 = 1. Setting Gate0 = 1 allows the timer to be
controlled by external input INT0 to facilitate pulse width
measurements. TR0 is a control bit in the Timer/Counter 0 and
Timer/Counter 1 Control SFR (TCON, 0x88); the Gate0/Gate1
bits are in the Timer/Counter 0 and Timer/Counter 1 Mode SFR
(TMOD, 0x89). The 13-bit register consists of all eight bits of
Timer 0 High Byte SFR (TH0, 0x8C) and the lower five bits of
Timer 0 Low Byte SFR (TL0, 0x8A). The upper three bits of the
TL0 SFR are indeterminate and should be ignored. Setting the
run flag (TR0) does not clear the registers.
Mode 1 (16-Bit Timer/Counter)
Mode 1 is the same as Mode 0 except that the Mode 1 timer
register runs with all 16 bits. Mode 1 is shown in Figure 83.
f
P0.6/T0
P0.6/T0
f
CORE
GATE
CORE
GATE
I NT0
INT
0
TR0
TR0
Figure 82. Timer/Counter 0, Mode 0
Figure 83. Timer/Counter 0, Mode 1
C/T0 = 0
C/T0 = 1
C/T0 = 0
C/T0 = 1
CONTROL
CONTROL
(5 BITS)
(8 BITS)
TL0
TL0
(8 BITS)
(8 BITS)
TH0
TH0
TF0
TF0
ADE7518
INTERRUPT
INTERRUPT