ade7518 Analog Devices, Inc., ade7518 Datasheet - Page 66

• Manufacturer Part Number: ade7518
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc, And Lcd Driver
• Manufacturer: Analog Devices, Inc.

ADE7518
STANDARD 8052 SFRS
The standard 8052 special function registers include the ACC,
B, PSW, DPTR, and SP SFRs described in the Basic 8052 Registers
section. The standard 8052 SFRs also define the timers, the
serial port interface, the interrupts, the I/O ports, and the
power-down modes.
Timer SFRs
The 8052 contains three 16-bit timers: the identical Timer0 and
Timer1, as well as a Timer2. These timers can also function as
event counters. Timer2 has a capture feature where the value of
the timer can be captured in two 8-bit registers upon the asser-
tion of an external input signal (see Table 91 and the Timers
section).
Serial Port SFRs
The full-duplex serial port peripheral requires two registers:
one for setting up the baud rate and other communication
parameters, and another for the transmit/receive buffer. The
ADE7518 also has enhanced serial port functionality with a
dedicated timer for baud rate generation with a fractional
divisor and additional error detection. See Table 120 and the
UART Serial Interface section.
Interrupt SFRs
There is a two-tiered interrupt system standard in the 8052 core.
The priority level for each interrupt source is individually selecta-
ble as high or low. The ADE7518 enhances this interrupt system
by creating, in essence, a third interrupt tier for the highest
priority, the power supply management (PSM) interrupt (see
the Interrupt System section).
I/O Port SFRs
The 8052 core supports four I/O ports, Port 0 through Port 3,
where Port 0 and Port 2 are typically used to access external
code and data spaces. The ADE7518, unlike standard 8052
products, provides internal nonvolatile flash memory so that an
external code space is unnecessary. The on-chip LCD driver
requires many pins, some of which are dedicated for LCD
functionality, and others that can be configured as LCD or
general-purpose inputs/outputs. Due to the limited number of
I/O pins, the ADE7518 does not allow access to external code
and data spaces.
The ADE7518 provides 20 pins that can be used for general-
purpose I/O. These pins are mapped to Port 0, Port 1, and Port 2.
They are accessed through three bit-addressable 8052 SFRs, P0,
P1, and P2. Another enhanced feature of the ADE7518 is that
the weak pull-ups that are standard on 8052 Port 1, Port 2, and
Port 3 can be disabled to make open-drain outputs, as is standard
on Port 0. The weak pull-ups can be enabled on a pin-by-pin
basis (see the I/O Ports section).
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Program Control Register (PCON, 0x87)
The 8052 core defines two power-down modes: power-down
and idle. The ADE7518 enhances the power control capability
of the traditional 8052 MCU with additional power management
functions. The Power Control SFR (POWCON, 0xC5) is used
to define power control-specific functionality for the ADE7518.
The Program Control SFR (PCON, 0x87) is not bit addressable
(see the Power Management section).
The ADE7518 has many other peripherals not standard to the
8052 core, including
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MEMORY OVERVIEW
The ADE7518 contains the following memory blocks:
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The 256 bytes of general-purpose RAM share the upper 128 bytes
of its address space with special function registers. All of the
memory spaces are shown in Figure 69. The addressing mode
specifies which memory space to access.
General-Purpose RAM
General-purpose RAM resides in the 0x00 through 0xFF
memory locations and contains the register banks.
Address 0x80 through Address 0xFF of general-purpose RAM
are shared with the special function registers. The mode of
addressing determines which memory space is accessed, as
shown in Figure 70.
BITS IN PSW
SELECTED
ADE energy measurement DSP
RTC
LCD driver
Battery switchover/power management
SPI/I
Flash memory controller
Watchdog timer
16 kB of on-chip Flash/EE program and data memory
256 bytes of general-purpose RAM
256 bytes of internal extended RAM (XRAM)
BANKS
VIA
2
C communication
Figure 69. Lower 128 Bytes of Internal Data Memory
11
10
01
00
0x30
0x20
0x18
0x10
0x08
0x 00
0x7F
0x2F
0x1F
0x0F
0x17
0x07
BIT-ADDRESSABLE
(BIT ADDRESSES)
FOUR BANKS OF EIGHT
REGISTERS R0 TO R7
GENERAL-PURPOSE
AREA
RESET VALUE OF
STACK POINTER