ade7518 Analog Devices, Inc., ade7518 Datasheet
ade7518
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ade7518 Summary of contents
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... Memory flash memory, 512 bytes RAM Development tools Single-pin emulation IDE-based assembly and C-source debugging , active, reactive, rms One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ADE7518 2 C, and watchdog timer www.analog.com ©2009 Analog Devices, Inc. All rights reserved. ...
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... ADE7518 TABLE OF CONTENTS General Features ............................................................................... 1 Energy Measurement Features ........................................................ 1 Microprocessor Features .................................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Functional Block Diagram .............................................................. 4 Specifications ..................................................................................... 5 Energy Metering ........................................................................... 5 Analog Peripherals ....................................................................... 6 Digital Interface ............................................................................ 7 Timing Specifications .................................................................. 9 Absolute Maximum Ratings .......................................................... 14 Thermal Resistance .................................................................... 14 ESD Caution ................................................................................ 14 Pin Configuration and Function Descriptions ........................... 15 Typical Performance Characteristics ........................................... 17 Terminology ...
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... I/O Ports ......................................................................................... 121 Parallel I/O ................................................................................. 121 I/O Registers .............................................................................. 122 Port 0 ........................................................................................... 125 Port 1 ........................................................................................... 125 Port 2 ........................................................................................... 125 Determining the Version of the ADE7518 ................................ 126 Outline Dimensions ...................................................................... 127 Ordering Guide ......................................................................... 127 Rev Page 3 of 128 ADE7518 ...
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... UART, and an SPI or I ADE core reduces the program memory size requirement, making it easy to integrate complicated design into flash memory. The ADE7518 also includes a 108-segment LCD driver. This driver generates waveforms capable of driving LCDs up to 3.3 V. FUNCTIONAL BLOCK DIAGRAM ...
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... Over a dynamic range of 500 25°C V − V differential input − I differential input P N PGA1 = PGA2 = 1 PGA1 = 0 0 Voltage channel = 0 − 400 mV peak, I − PGA1 = 2 sine wave If CF1 or CF2 frequency, >5. CF1 or CF2 frequency, <5.55 Hz ADE7518 = 250 mV, N ...
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... ADE7518 ANALOG PERIPHERALS Table 2. Parameter POWER-ON RESET (POR) V POR DD Detection Threshold POR Active Timeout Period V POR SWOUT Detection Threshold POR Active Timeout Period V POR INTD Detection Threshold POR Active Timeout Period V POR INTA Detection Threshold POR Active Timeout Period BATTERY SWITCHOVER ...
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... J Crystal = 32.768 kHz and CD[2:0] = 0b000 Crystal = 32.768 kHz and CD[2:0] = 0b111 V = 3.3 V ± 3.3 V ± 2. PSM0 code execution 2. PSM0 code execution DD Wake-up event to PSM1 code execution PSM0 code execution 2.4 V BAT ADE7518 = 3.3 V ...
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... ADE7518 Parameter POWER SUPPLY CURRENTS Current in Normal Mode (PSM0) Current in PSM1 Current in PSM2 POWER SUPPLY CURRENTS Current in Normal Mode (PSM0) 1 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C. 2 Retention lifetime equivalent at junction temperature (T 3 Test performed with all the I/Os set to a low output level ...
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... The ADE7518 internal PLL locks onto a multiple (512 times) of the 32.768 kHz external crystal frequency to provide a stable 4.096 MHz internal clock for the system. The core can operate at this frequency binary submultiple defined by the CD[2:0] bits, selected via the POWCON SFR (see Table 24). ...
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... ADE7518 Table 6. SPI Master Mode Timing (SPICPHA = 1) Parameters Parameter Description t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data input setup time before SCLK edge DSU t Data input hold time after SCLK edge ...
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... MSB IN BITS [6:1] t DHD Figure 5. SPI Master Mode Timing (SPICPHA = 0) Rev Page 11 of 128 Typ Max 1 (SPIR + 1) × CORE CORE 1 1 (SPIR + 1) × t CORE CORE 3 × LSB LSB IN ADE7518 Unit CORE ...
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... ADE7518 Table 8. SPI Slave Mode Timing (SPICPHA = 1) Parameters Parameter Description SCLK edge SS t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data input setup time before SCLK edge DSU t Data input hold time after SCLK edge ...
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... DHD Figure 7. SPI Slave Mode Timing (SPICPHA = 0) Rev Page 13 of 128 Min Typ Max 145 1 6 × t CORE 1 6 × t CORE × 0.5 CORE SFS LSB LSB IN ADE7518 Unit μ ...
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... ADE7518 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 10. Parameter V to DGND DGND BAT V to DGND DCIN Input LCD Voltage to AGND, LCDVA, 1 LCDVB, LCDVC Analog Input Voltage to AGND and I N Digital Input Voltage to DGND Digital Output Voltage to DGND ...
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... TOP VIEW 9 (Not to Scale Figure 8. Pin Configuration . A resistor should be connected between LCDVC and LCDVB to DD Rev Page 15 of 128 ADE7518 INT0 48 XTAL1 47 XTAL2 46 45 BCTRL/INT1/P0.0 SDEN/P2 P0.2/CF1/RTCCAL 42 P0.3/CF2 P0.4/MOSI/SDATA 41 P0 ...
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... A crystal can be connected across this pin and XTAL1 (see the XTAL1 pin description) to provide a clock source for the ADE7518. The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1 or by the gate oscillator circuit. An internal 6 pF capacitor is connected to this pin. ...
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... Temperature with Internal Reference 2.0 MID CLASS C GAIN = 1 INTERNAL REFERENCE 1.5 1.0 +25° +85° 0.5 +25° 0.5 +85° 0.5 0 –40° –0.5 –40° 0.5 –1.0 –1.5 MID CLASS C –2.0 0 CURRENT CHANNEL (% of Full Scale) Power Factor with Internal Reference ADE7518 100 100 100 ...
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... ADE7518 0.5 GAIN = 1 INTERNAL REFERENCE 0.4 0.3 0 3.3V rms I ; 3.3V rms 0 3.43V rms 0 –0 3.13V rms –0.2 –0.3 –0.4 –0.5 0.1 1 CURRENT CHANNEL (% of Full Scale) Figure 15. Voltage and Current RMS Error as a Percentage of Reading (Gain = 1) over Power Supply with Internal Reference 1.0 GAIN = 1 INTERNAL REFERENCE 0.8 0.6 MID CLASS B 0 ...
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... CURRENT CHANNEL (% of Full Scale) Temperature with Internal Reference 2.0 GAIN = 16 MID CLASS C INTERNAL REFERENCE 1.5 1.0 –40° +25° 0.5 –40° 0.5 0 +85° 0.5 +25° 0.5 +85° MID CLASS C 0 CURRENT CHANNEL (% of Full Scale) Power Factor with Internal Reference ADE7518 100 100 100 ...
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... Hz. Power Supply Rejection (PSR) PSR quantifies the ADE7518 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (3 taken. ...
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... TL1 Table 102 TL0 Table 94 TMOD Table 89 TCON Table 88 PCON Table 24 Table 105 DPH DPL Table 65 SP Table 87 P0 Rev Page 21 of 128 ADE7518 Address Details 0xBE Table 86 0xBD Table 85 0xBC Table 84 0xBB Table 83 0xBA Table 82 0xB9 Table 81 0xB8 Table 59 0xB4 ...
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... ADE7518 POWER MANAGEMENT The ADE7518 has elaborate power management circuitry that manages the regular power supply to battery switchover and power supply failures. The power management functionalities can be accessed directly through the 8052 SFRs (see Table 14). Table 14. Power Management SFRs SFR Address ...
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... Battery switchover enabled on low V Battery switchover disabled power supply is ready for operation. DD Result GPIO RxD with wake-up disabled RxD with wake-up enabled monitor flag (FVDCIN) is set. DCIN Rev Page 23 of 128 ADE7518 power supply has been restored BAT DD switches from SWOUT DD BAT ...
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... ADE7518 Table 21. Scratch Pad 2 SFR (SCRATCH2, 0xFC) Bit Mnemonic Default Description SCRATCH2 0 Value can be written/read in this register. This value is maintained in all the power saving modes. Table 22. Scratch Pad 3 SFR (SCRATCH3, 0xFD) Bit Mnemonic Default Description SCRATCH3 0 Value can be written/read in this register. This value is maintained in all the power saving modes. ...
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... BAT battery switchover option ensures a stable power supply to the for full operation. DD ADE7518, as long as the external battery voltage is above 2. allows continuous code execution even while the internal power supply is switching from V , which is used to derive the energy metering ADCs are not available when V ...
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... ADE7518 POWER SUPPLY MANAGEMENT (PSM) INTERRUPT The power supply management (PSM) interrupt alerts the 8052 core of power supply events. The PSM interrupt is disabled by default. Setting the EPSM bit in the Interrupt Enable and Priority 2 SFR (IEIP2, 0xA9) enables the PSM interrupt (see Table 60). ...
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... Battery Switchover and Power Supply Restored PSM Interrupt The ADE7518 can be configured to generate a PSM interrupt when the source of V changes from V SWOUT battery switchover. Setting the EBSO bit in the Power Management Interrupt Enable SFR (IPSME, 0xEC) enables this event to generate a PSM interrupt (see Table 19). ...
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... voltage regulator IC. The preregulated dc voltage, typically can be connected to V tor divider. A 3.6 V battery can be connected to V shows how the ADE7518 power supply inputs are set up in this application. Figure 30 shows the sequence of events that occurs if the main power supply generated by the PSU starts to fail in the power meter application shown in Figure 29 ...
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... V and V above 2. DCIN DD switches SWOUT EVENT IF SWITCHOVER ON LOW V DCIN ENABLED, AUTOMATIC BATTERY SWITCHOVER V CONNECTED TO V SWOUT BSO EVENT (FBSO = Enabled for Battery Switchover DD DCIN V EVENT DCIN 130ms MIN PSM0 PSM1 OR PSM2 PSM0 PSM1 OR PSM2 ADE7518 IS BAT ...
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... These SFRs can be used to save data from PSM0 or PSM1 when entering PSM2 (see Table 20 to Table 23). In PSM2, the ADE7518 maintains some SFRs (see Table 26). The SFRs that are not listed in this table should be restored when the part enters PSM0 or PSM1 from PSM2. ...
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... The RTC interrupt needs to be serviced and acknowledged prior to entering PSM2 mode. Alarm IRTC An alarm can be set to wake the ADE7518 after the desired amount of time. The RTC alarm is enabled by setting the ALARM bit in the RTC Configuration SFR (TIMECON, 0xA1). The RTC interrupt needs to be serviced and acknowledged prior to entering PSM2 mode ...
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... MCU core. Events capable of waking the MCU can be enabled (see the 3.3 V Peripherals and Wake-Up Events section). Servicing Wake-Up Events (PSM2 to PSM1) The ADE7518 may need to wake up from PSM2 to service wake-up events (see the 3.3 V Peripherals and Wake-Up Events section). PSM1 code execution begins at the power-on reset vector ...
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... ENERGY MEASUREMENT The ADE7518 offers a fixed function, energy measurement, digital processing core that provides all the information needed to measure energy in single-phase energy meters. The part provides two ways to access the energy measurements: direct access through SFRs for time sensitive information and indirect access through address and data SFR registers for the majority of energy measurements ...
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... ADE7518 Table 29. Energy Measurement SFRs Address R/W Mnemonic 0x91 R/W MADDPT 0x92 R/W MDATL 0x93 R/W MDATM 0x94 R/W MDATH 0xD1 R VRMSL 0xD2 R VRMSM 0xD3 R VRMSH 0xD4 R IRMSL 0xD5 R IRMSM 0xD6 R IRMSH 0xD9 R/W MIRQENL 0xDA R/W MIRQENM 0xDB R/W MIRQENH 0xDC R/W MIRQSTL 0xDD R/W MIRQSTM 0xDE R/W MIRQSTH 0xE2 R WAV1L ...
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... S 0 Sets voltage rms offset register Sets WATT energy scaling register Sets VAR energy scaling register Sets VA energy scaling register Sets CF1 numerator register. U 0x003F Sets CF1 denominator register. Rev Page 35 of 128 ADE7518 . rms . rms . rms ...
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... ADE7518 Address Length MADDPT[6:0] Mnemonic R/W (Bits) 0x29 CF2NUM R/W 16 0x2A CF2DEN R/W 16 0x3B Reserved 0x3C Reserved 0x3D Reserved 0x3E Reserved 0x3F Reserved ENERGY MEASUREMENT INTERNAL REGISTERS DETAILS Table 31. MODE1 Register (0x0B) Bit Mnemonic Default 7 SWRST 0 6 DISZXLPF 0 5 Reserved 0 4 SWAPBITS 0 3 PWRDN ...
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... APNOLOAD[1:0] Result 00 No load detection disabled 01 No load detection enabled with threshold = 0.015% of full scale 10 No load detection enabled with threshold = 0.0075% of full scale 11 No load detection enabled with threshold = 0.0037% of full scale Rev Page 37 of 128 ADE7518 /5 = 819.2 kHz) CORE ...
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... ADE7518 Table 35. ACCMODE Register (0x0F) Bit Mnemonic Default Description Reserved 0 These bits should be left at their default value for proper operation. 5 VARSIGN 0 Configuration bit to select the event that triggers a reactive power sign interrupt. If set to 0, VARSIGN interrupt occurs when reactive power changes from positive to negative. If this bit is set to 1, VARSIGN interrupt occurs when reactive power changes from negative to positive ...
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... When this bit is set, the CYCEND flag set creates a pending ADE interrupt to the 8052 core. 1 ZXTO When this bit is set, the ZXTO flag set creates a pending ADE interrupt to the 8052 core When this bit is set, the ZX flag set creates a pending ADE interrupt to the 8052 core. Rev Page 39 of 128 ADE7518 ...
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... ADE7518 ANALOG INPUTS The ADE7518 has two fully differential voltage input channels. The maximum differential input voltage for input pairs V and ±0 Each analog input channel has a programmable gain amplifier (PGA) with possible gain selections and 16. The gain selections are made by writing to the GAIN register (see Table 36 and Figure 36) ...
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... Oversampling means that the signal is sampled at a rate (frequency) that is many times higher than the bandwidth of interest. For example, the sampling rate in the ADE7518 is 4.096 MHz/5, or 819.2 kHz, and the band of interest kHz. Oversampling has the effect of spreading the quantization ...
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... Figure 39. ADC and Signal Processing in Current Channel Outline Dimensions ADC Transfer Function Both ADCs in the ADE7518 are designed to produce the same output code for the same input signal level. With a full-scale signal on the input of 0.4 V and an internal reference of 1.2 V, the ADC output code is nominally 2,147,483, or 0x20C49B. The maximum code from the ADC is ± ...
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... VOLTAGE CHANNEL WAVEFORM DATA RANGE MODE1[6] 0x28F5 0x0000 0xD70B Figure 41. ADC and Signal Processing in Voltage Channel Rev Page 43 of 128 ADE7518 ) rms ZX DETECTION ZX SIGNAL DATA RANGE FOR 60Hz SIGNAL 0x1DD0 0x0000 0xE230 ZX SIGNAL DATA RANGE FOR 50Hz SIGNAL 0x2037 ...
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... ADE7518 POWER QUALITY MEASUREMENTS Zero-Crossing Detection Each ADE7518 has a zero-crossing detection circuit on the voltage channel. This zero crossing is used to produce a zero- crossing internal signal (ZX) and is used in calibration mode. The zero-crossing is generated by default from the output of LPF1. This filter has a low cutoff frequency and is intended for 50 Hz and 60 Hz systems ...
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... Line Voltage SAG Detection In addition to detection of the loss of the line voltage signal (zero crossing), the ADE7518 can also be programmed to detect when the absolute value of the line voltage drops below a certain peak value for a number of line cycles. This condition is illu- strated in Figure 44. ...
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... For time sampling signals, rms calculation involves squaring the signal, taking the average, and obtaining the square root. The ADE7518 implements this method by serially squaring the input, averaging them, and then taking the square root of the average. The averaging part of this signal processing is done by implement- ing a low-pass filter (LPF3 in Figure 47, Figure 48, and Figure 50). This LPF has a − ...
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... Figure 48. Current Channel RMS Signal Processing with PGA1 = 16. The current rms measurement provided in the ADE7518 is accurate to within 0.5% for signal inputs between full scale and full scale/500. The conversion from the register value to amps must be done externally in the microprocessor using an amps/LSB constant ...
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... P is referred to as the active or real power. Note that the active power is equal to the dc component of the instantaneous power signal p(t) in Equation 9, that is, VI. This is the relationship used to calculate active power in the ADE7518. The instantaneous power signal p(t) is generated by multiplying the current and voltage signals. The dc component of the instantaneous power signal is then extracted by LPF2 (low-pass filter) to obtain the active power information ...
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... Therefore, the power offset correction resolution is 0.000464%/LSB (0.119%/256) at −60 dB. Active Power Sign Detection The ADE7518 detects a change of sign in the active power. The APSIGN flag in the Interrupt Status 1 SFR (MIRQSTL, 0xDC) records when a change of sign has occurred according to Bit APSIGN in the ACCMODE register (0x0F) ...
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... When both bits are cleared, the addition is signed and, therefore, negative energy is subtracted from the active energy contents. When both bits are set, the ADE7518 is set the more restrictive mode, the positive-only accumulation mode. When POAM in the ACCMODE register (0x0F) is set, only posi- tive power contributes to the active energy accumulation ...
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... The watt gain register is used to carry out power calibration in the ADE7518. As shown, the fastest integration time occurs when the watt gain register is set to maximum full scale, that is, 0x7FF. ...
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... INTERRUPT STATUS REGISTERS Figure 55. Energy Accumulation in Watt-Absolute Accumulation Mode Active Energy Pulse Output All of the ADE7518 circuitry has a pulse output whose frequency is proportional to active power (see the Active Power Calculation section). This pulse frequency output uses the calibrated signal from the WGAIN register output, and its behavior is consistent with the setting of the active energy accumulation mode in the ACCMODE register (0x0F) ...
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... Rev Page 53 of 128 = ω sin( t θ ω sin π ⎛ ⎞ ω ⎜ ⎟ sin t ⎝ ⎠ 2 ωt + θ ∫ = θ sin ADE7518 (19) (20) (21) (22) ...
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... SAVARM and ABSVARM bits in the ACCMODE register (0x0F). Negative When both bits are cleared, the addition is signed and, therefore, negative energy is subtracted from the reactive energy contents. When both bits are set, the ADE7518 is set the more restrictive mode, the absolute accumulation mode. Rev Page 54 of 128 ...
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... Conversely, if the power is negative, the reactive energy register underflows to full-scale positive (0x7FFFFF) and continues to decrease in value. By using the interrupt enable register, the ADE7518 can be configured to issue an ADE interrupt to the 8052 core when the reactive energy register is half full (positive or negative) or when an overflow or underflow occurs ...
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... The ADE7518 reactive energy default accumulation mode is a signed accumulation based on the reactive power information. VAR Antitamper Accumulation Mode The ADE7518 is placed in VAR antitamper accumulation mode by setting the SAVARM bit in the ACCMODE register (0x0F). In this mode, the reactive power is accumulated depending on the sign of the active power ...
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... LVARHR register for an integral number of line cycles, as shown in Figure 61. The number of half-line cycles is specified in the LINCYC register. The ADE7518 can accumulate active power for up to 65,535 half-line cycles. Because the reactive power is integrated on an integer number ...
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... Similarly, 0x800 = –2047d (signed twos complement) and power (27) output is scaled by –50%. Each LSB represents 0.0244% of the power output. The apparent power is calculated with the current (28) and voltage rms values obtained in the rms blocks of the ADE7518. ω + θ ...
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... Apparent Energy Apparent Power The ADE7518 achieves the integration of the apparent power signal by continuously accumulating the apparent power signal in an internal 48-bit register. The apparent energy register (VAHR[23:0]) represents the upper 24 bits of this internal register. This discrete time accumulation or summation is equivalent to integration in continuous time ...
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... FROM VOLTAGE CHANNEL ADC Apparent Power No Load Detection The ADE7518 includes a no load threshold feature on the apparent power that eliminates any creep effects in the meter. The ADE7518 accomplishes this by not accumulating energy if the multiplier output is below the no load threshold. When the ...
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... The maximum output frequency with ac input signals at full scale and CFxNUM = 0x00 and CFxDEN = 0x00 is approximately 21.1 kHz. , depending on The ADE7518 incorporates two registers per DFC, CFxNUM[15:0] rms and CFxDEN[15:0], to set the CFx frequency. These are unsigned 16-bit registers that can be used to adjust the CFx frequency to a wide range of values ...
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... VA = 0.9977 × WATT VA = 1.0015 × WATT ENERGY MEASUREMENT INTERRUPTS The energy measurement part of the ADE7518 has its own interrupt vector for the 8052 core, Vector Address 0x004B (see the Interrupt Vectors section). The bits set in the Interrupt Enable 1 SFR (MIRQENL, 0xD9), Interrupt Enable 2 SFR ...
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... MCU CORE ARCHITECTURE The ADE7518 has an 8052 MCU core and uses the 8051 instruc- tion set. Some of the standard 8052 peripherals, such as the UART, have been enhanced. This section describes the standard 8052 core and its enhancements used in the ADE7518. ...
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... ADE7518 Table 47. Program Control SFR (PCON, 0x87) Bit Default Description 7 0 SMOD Bit. Double baud rate control Reserved. Should be left cleared. Table 48. Data Pointer Low SFR (DPL, 0x82) Bit Default Description Contain the low byte of the data pointer. ...
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... DPH, DPL two independent 8-bit registers (DPH, DPL). See Table 48 and Table 49. The ADE7518 supports dual data pointers. See the Dual Data Pointers section. Note that the Dual Data Pointers section is the only section in the data sheet where the main and shadow data pointers are distinguished ...
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... I/O. These pins are mapped to Port 0, Port 1, and Port 2. They are accessed through three bit-addressable 8052 SFRs, P0, P1, and P2. Another enhanced feature of the ADE7518 is that the weak pull-ups that are standard on 8052 Port 1, Port 2, and Port 3 can be disabled to make open-drain outputs standard on Port 0 ...
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... Boolean and program branching instructions. These SFRs are labeled as bit-addressable and the bit addresses are given in the SFR Mapping section. Extended Internal RAM (XRAM) The ADE7518 provides 256 bytes of extended on-chip RAM, ONLY which is located in Address 0x0000 through Address 0x00FF in the extended RAM space. No external RAM is supported. To select the extended RAM memory space, the extended indirect addressing modes are used ...
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... Extended Indirect Addressing The internal extended RAM is accessed through a pointer to the address in indirect addressing mode. The ADE7518 has 256 bytes of internal extended RAM, accessed through MOVX instructions. External memory is not supported on the devices. In extended indirect addressing mode, a register holds the address of the byte of extended RAM ...
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... XRL dir, A Exclusive direct byte XRL A, dir Exclusive OR indirect memory to A XRL dir, #data Exclusive OR immediate data to direct CLR A Clear A CPL A Complement A SWAP A Swap nibbles Rotate A left Rev Page 69 of 128 ADE7518 Bytes Cycles ...
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... ADE7518 Mnemonic Description RLC A Rotate A left through carry RR A Rotate A right RRC A Rotate A right through carry Data Transfer MOV A, Rn Move register to A MOV A, @Ri Move indirect memory to A MOV Rn, A Move A to register MOV @Ri, A Move A to indirect memory MOV A, dir ...
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... Used to indicate an overflow for signed addition. This flag is set if two positive operands yield a negative result or if two negative operands yield a positive result. AC Set if there is a carry out of Bit 3. Cleared otherwise. Rev Page 71 of 128 ADE7518 Bytes Cycles ...
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... ADE7518 SUBB A, Source This instruction subtracts the source byte and the carry (borrow) flag from the accumulator. It references the carry (borrow) status flag. Affected Status Flags C Set if there is a borrow needed for Bit 7. Cleared otherwise. Used to indicate an overflow if the operands are unsigned. ...
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... DUAL DATA POINTERS The ADE7518 incorporates two data pointers. The second data pointer is a shadow data pointer and is selected via the Data Pointer Control SFR (DPCON, 0xA7). DPCON features automatic hard- ware postincrement and postdecrement, as well as an automatic data pointer toggle. ...
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... See the 3.3 V Peripherals and Wake-Up Events section to learn more about events that can wake the 8052 core from PSM2. The ADE7518 provides 12 interrupt sources with three priority levels. The power management interrupt is at the highest priority level. The other two priority levels are configurable through the Interrupt Priority SFR (IP, 0xB8) and the Interrupt Enable and Priority 2 SFR (IEIP2, 0xA9) ...
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... C Interrupt. Set by the user. Description Power Supply Management Interrupt. RTC Interval Timer Interrupt. ADE Energy Measurement Interrupt. Watchdog Timer Overflow Interrupt. External Interrupt 0. Timer/Counter 0 Interrupt. External Interrupt 1. Timer/Counter 1 Interrupt. 2 SPI/I C Interrupt. UART Serial Port Interrupt. Timer/Counter 2 Interrupt. Rev Page 75 of 128 ADE7518 ...
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... A functional block diagram of the interrupt system is shown in Figure 75. Note that the PSM interrupt is the only interrupt in the highest priority level external wake-up event occurs to wake the ADE7518 from PSM2, a pending external interrupt is generated. When the EX0 or EX1 bit in the Interrupt Enable SFR (IE, 0xA8) is set to enable external interrupts, the program counter is loaded with the IE0 or IE1 interrupt vector ...
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... IP/IEIP2 REGISTERS IN/OUT LATCH RESET MIRQSTL.7 PSM2 IE0 PSM2 IE1 IN/OUT LATCH RESET INDIVIDUAL INTERRUPT ENABLE GLOBAL INTERRUPT ENABLE (EA) Figure 75. Interrupt System Functional Block Diagram Rev Page 77 of 128 ADE7518 PRIORITY LEVEL LOW HIGH HIGHEST INTERRUPT POLLING SEQUENCE LEGEND AUTOMATIC CLEAR SIGNAL ...
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... ADE7518 INTERRUPT VECTORS When an interrupt occurs, the program counter is pushed onto the stack, and the corresponding interrupt vector address is loaded into the program counter. When the interrupt service routine is complete, the program counter is popped off the stack by a RETI instruction. This allows program execution to resume from where it was interrupted ...
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... WATCHDOG TIMER The watchdog timer generates a device reset or interrupt within a reasonable amount of time if the ADE7518 enters an erroneous state, possibly due to a programming error or electrical noise. The watchdog is enabled by default with a timeout of two seconds and creates a system reset if not cleared within two seconds. The watchdog function can be disabled by clearing the watchdog enable bit (WDE) in the Watchdog Timer SFR (WDCON, 0xC0) ...
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... ADE7518 Table 66. Watchdog and Flash Protection Byte in Flash (Flash Address = 0x3FFA) Bit Mnemonic Default 7 WDPROT_PROTKY7 PROTKY[6:0] 0xFF Writing to the Watchdog Timer SFR (WDCON, 0xC0) Writing data to the WDCON SFR involves a double instruction sequence. The WDWR bit must be set and the following instruction must be a write instruction to the WDCON SFR ...
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... LCD DRIVER Using shared pins, the LCD module is capable of directly driving an LCD panel of 17 × 4 segments without compromising any ADE7518 functions capable of driving LCDs with 2×, 3×, and 4× multiplexing. The LCD waveform voltages are generated through an external resistor ladder. ...
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... ADE7518 Table 69. LCD Configuration X SFR (LCDCONX, 0x9C) Bit Mnemonic Default 7 Reserved 0 6 EXTRES Reserved 0 Table 70. LCD Configuration Y SFR (LCDCONY, 0xB1) Bit Mnemonic Default 7 Reserved 0 6 INV_LVL Reserved 0 1 UPDATEOVER 0 0 REFRESH 0 Table 71. LCD Clock SFR (LCDCLK, 0x96) ...
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... LCD 1 170.7 512 128 1 113.8 341.3 85.3 85.3 256 64 68.3 204.8 51.2 56.9 170.7 42.7 48.8 146.3 36.6 42.7 128 32 37.9 113.8 28.5 34.1 102.4 25.6 31 93.1 23.25 28.4 85.3 21.35 26.3 78.8 19.7 24.4 73.1 18.3 22.8 68.3 17. 4× Multiplexing Frame Rate (Hz) f (Hz) Frame Rate (Hz) LCD 42.7 128 32 21 ADE7518 1 ...
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... ADE7518 Table 75. LCD Pointer SFR (LCDPTR, 0xAC) Bit Mnemonic Default 7 0 R/W 6 Reserved ADDRESS 0 Table 76. LCD Data SFR (LCDDAT, 0xAE) Bit Mnemonic Default LCDDATA 0 Table 77. LCD Segment Enable 2 SFR (LCDSEGE2, 0xED) Bit Mnemonic Default Reserved 0 3 FP19EN 0 2 FP18EN ...
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... FP14 FP14 FP12 FP12 FP12 FP10 FP10 FP10 FP8 FP8 FP8 FP6 FP6 FP6 FP4 FP4 FP4 FP2 FP2 FP2 FP0 FP0 FP0 ADE7518 1, 2 COM0 FP28 FP26 FP24 FP22 FP20 FP18 FP16 FP14 FP12 FP10 FP8 FP6 FP4 FP2 FP0 ...
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... ADE7518 LCD EXTERNAL CIRCUITRY The voltage generation selection is made by setting Bit EXTRES in the LCD Configuration X SFR (LCDCONX, 0x9C). This bit is cleared by default and needs to be set to enable an external resistor ladder. External Resistor Ladder To enable the external resistor ladder, set the EXTRES bit in the LCD Configuration X SFR (LCDCONX, 0x9C) ...
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... Flash/EE Memory Reliability The flash memory arrays on the ADE7518 are fully qualified for two key Flash/EE memory characteristics: Flash/EE memory cycling endurance and Flash/EE memory data retention. ...
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... ADE7518 FLASH MEMORY ORGANIZATION The flash memory provided by the ADE7518 are seg- mented into 32 pages of 512 bytes each the user to decide which flash memory to allocate for data memory recommended that each page be dedicated solely to program memory or to data memory. Doing so prevents the program counter from being loaded with data memory instead of an operations code from the program memory ...
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... All peripherals, such as timers and counters, continue to operate as configured throughout the flash memory access. PROTB0.6 PROTB0.5 PROTB0.4 Page 6 Page 5 Page 4 PROTB1.6 PROTB1.5 PROTB1.4 Page 14 Page 13 Page 12 Rev Page 89 of 128 ADE7518 PROTB0.3 PROTB0.2 PROTB0.1 Page 3 Page 2 Page 1 PROTB1.3 PROTB1.2 PROTB1.1 Page 11 Page 10 Page 9 PROTB0.0 Page 0 PROTB1 ...
Page 90
... ADE7518 Table 87. Flash Read Protection SFR (PROTR, 0xBF) Bit Mnemonic Default Description PROTR 0xFF This SFR is used to write the read protection bits for Page 0 to Page 31 of the flash memory (see the Protecting the Flash Memory section). Clearing the bits enables the protection. ...
Page 91
... Also, note that the most significant bit of Address 0x3FFA is used to enable a lock mechanism for the watchdog settings (see the Watchdog Timer section for more information). Run the protection command by writing 0x08 to the ECON register. Reset the chip to activate the new protection. ADE7518 ...
Page 92
... This allows the user to download code to the full flash memory while the device is in-circuit in its target application hardware. Protection configured in the last page of the ADE7518 affects whether flash memory can be accessed in serial download mode. Read protected pages cannot be read. Write/erase protected pages cannot be written or erased ...
Page 93
... TIMERS The ADE7518 has three 16-bit timer/counters: Timer/Counter 0, Timer/Counter 1, and Timer/Counter 2. The timer/counter hardware is included on chip to relieve the processor core of overhead inherent in implementing timer/counter functionality in software. Each timer/counter consists of two 8-bit registers: THx and TLx ( 2). All three timers can be configured to operate as timers or as event counters ...
Page 94
... ADE7518 Table 93. Timer/Counter 0 and Timer/Counter 1 Control SFR (TCON, 0x88) Bit Address Mnemonic Default 7 0x8F TF1 0 6 0x8E TR1 0 5 0x8D TF0 0 4 0x8C TR0 0x8B IE1 0x8A IT1 0x89 IE0 0x88 IT0 0 1 These bits are not used to control Timer/Counter 0 and Timer/Counter 1 but are instead used to control and monitor the external INT0 and INT1 interrupt pins. ...
Page 95
... Mode 1 is the same as Mode 0 except that the Mode 1 timer register runs with all 16 bits. Mode 1 is shown in Figure 83. f CORE C/ C/ P0.6/T0 TR0 GATE INT 0 Figure 83. Timer/Counter 0, Mode 1 Rev Page 95 of 128 ADE7518 INTERRUPT TL0 TH0 TF0 (5 BITS) (8 BITS) CONTROL INTERRUPT TL0 TH0 TF0 (8 BITS) ...
Page 96
... ADE7518 Mode 2 (8-Bit Timer/Counter with Autoreload) Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in Figure 84. Overflow from TL0 not only sets TF0 but also reloads TL0 with the contents of TH0, which is preset by software. The reload leaves TH0 unchanged. ...
Page 97
... P1.4/T2 CONTROL TR2 CAPTURE TRANSITION DETECTOR P1.3/ T2EX CONTROL EXEN2 Figure 87. Timer/Counter 2, 16-Bit Capture Mode Rev Page 97 of 128 TL2 TH2 (8 BITS) (8 BITS) RCAP2L RCAP2H TF2 TIMER INTERRUPT EXF2 TL2 TH2 TF2 (8 BITS) (8 BITS) TIMER INTERRUPT RCAP2L RCAP2H EXF2 ADE7518 ...
Page 98
... ADE7518 PLL The ADE7518 is intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple of this frequency to provide a stable 4.096 MHz clock for the system. The core can operate at this frequency or at binary submultiples allow power savings when maximum core performance is not required. The default core clock is the PLL clock divided ...
Page 99
... Rx with wake-up enabled Default Description 0 Set this bit to clear the PLL fault bit, PLL_FLT in the PERIPH register. A PLL fault is generated if a reset was caused because the PLL lost lock. 0 Reserved. Rev Page 99 of 128 ADE7518 . If this bit is set SWOUT SWOUT ...
Page 100
... ADE7518 REAL-TIME CLOCK The ADE7518 has an embedded real-time clock (RTC), as shown in Figure 88. The external 32.768 kHz crystal is used as the clock source for the RTC. Calibration is provided to compensate the nominal crystal frequency and for variations in the external crystal frequency over temperature. By default, the RTC is maintained active in all power saving modes ...
Page 101
... The ALARM flag is set after INTVAL counts and then another interval count starts. The ALARM flag is set after one time interval. Result The interval timer is disabled. The 8-bit interval timer counter is reset. Set this bit to enable the interval timer. Rev Page 101 of 128 ADE7518 ...
Page 102
... ADE7518 Table 114. Alarm Interval SFR (INTVAL, 0xA6) Bit Mnemonic Default Description INTVAL 0 The interval timer counts according to the time base established in the ITS[1:0] bits of the RTC Configuration SFR (TIMECON, 0xA1). Once the number of counts is equal to INTVAL, the ALARM flag is set and a pending RTC interrupt is created ...
Page 103
... RTC interrupt by servicing the event and clearing the appropriate flag in the RTC interrupt servicing routine. Note that if the ADE7518 is awakened by an RTC event, either by the MIDNIGHT event or the ALARM event, the pending RTC interrupt must be serviced before the device can go back to sleep again ...
Page 104
... ADE7518 Take care when changing the interval timer time base. The recommended procedure is as follows the Alarm Interval SFR (INTVAL, 0xA6) is going to be modified, write to this register first. Then, wait for one 128 Hz clock cycle to synchronize with the RTC, 64,000 cycles at a 4.096 MHz instruction cycle clock. ...
Page 105
... UART SERIAL INTERFACE The ADE7518 UART can be configured in one of four modes. • Shift register with baud rate fixed at f • 8-bit UART with variable baud rate • 9-bit UART with baud rate fixed at f • 9-bit UART with variable baud rate Variable baud rates are defined by using an internal timer to generate any rate between 300 baud/sec and 115,200 baud/sec ...
Page 106
... ADE7518 Table 122. Serial Port Buffer SFR (SBUF, 0x99) Bit Mnemonic Default SBUF 0 Table 123. Enhanced Serial Baud Rate Control SFR (SBAUDT, 0x9E) Bit Mnemonic Default 7 OWE SBTH[1: DIV[2:0] 000 Table 124. UART Timer Fractional Divider SFR (SBAUDF, 0x9D) ...
Page 107
... Rev Page 107 of 128 ADE7518 SBAUDF % Error 0x87 +0.16 0x87 +0.16 0x87 +0.16 0x87 +0.16 0xAB −0.31 0xAB −0.31 0xAB −0.31 0xAB −0.31 0xAB −0.31 0xAB −0.31 0xAB −0.31 0xAB − ...
Page 108
... ADE7518 UART OPERATION MODES Mode 0 (Shift Register with Baud Rate Fixed at f Mode 0 is selected when the SM0 and SM1 bits in the Serial Communications Control Register Bit Description SFR (SCON, 0x98) are cleared. In this shift register mode, serial data enters and exits through RxD. TxD outputs the shift clock. The baud rate is fixed at f /12 ...
Page 109
... Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in Timer/Counter 2 Control SFR (T2CON, 0xC8). The baud rates for transmit and receive can be simultaneously different. Setting RCLK and/or Rev Page 109 of 128 ADE7518 ⎛ ⎞ f ⎜ ...
Page 110
... UART is required. To address this problem, each ADE7518 has a dedicated baud rate timer (UART timer) specifically for generating highly accurate baud rates. The UART timer can be used instead of Timer 1 or Timer 2 for generating very accurate high speed UART baud rates, including 115,200 bps ...
Page 111
... RB8 bit is low. Break error detection not possible for a 9-bit 8052 UART because the stop bit is not recorded. The ADE7518 enhanced break error detection is available through the BE bit in the SBAUDT SFR. ⎞ The 8052 standard UART prevents overwrite errors by not ⎟ ...
Page 112
... ADE7518 SERIAL PERIPHERAL INTERFACE (SPI) The ADE7518 integrates a complete hardware serial peripheral interface on-chip. The SPI is full duplex so that eight bits of data are synchronously transmitted and simultaneously received. This SPI implementation is double buffered, allowing users to read the last byte of received data while a new byte is shifted in. ...
Page 113
... Master Mode, SPI SCLK Frequency. SPIR[1:0] Result 512 kHz (if f CORE 01 f /16 = 256 kHz (if f CORE 10 f /32 = 128 kHz (if f CORE kHz (if f CORE Rev Page 113 of 128 = 4.096 MHz). CORE = 4.096 MHz). CORE = 4.096 MHz). CORE = 4.096 MHz). CORE ADE7518 ...
Page 114
... ADE7518 Table 130. SPI Configuration SFR 2 (SPIMOD2, 0xE9) Bit Mnemonic Default Description 7 SPICONT 0 Master Mode, SPI Continuous Transfer Mode Enable Bit. SPICONT SPIEN 0 SPI Interface Enable Bit. SPIEN SPIODO 0 SPI Open-Drain Output Configuration Bit. SPIODO SPIMS_b 0 SPI Master Mode Enable Bit. ...
Page 115
... In both master and slave modes, the data is transmitted on one edge of the SCLK signal and sampled on the other important, therefore, that the SPICPHA and SPICPOL bits be configured the same for the master and slave devices. Rev Page 115 of 128 ADE7518 interrupt is ...
Page 116
... ADE7518 SS (Slave Select Pin) In SPI slave mode, a transfer is initiated by the assertion of SS low. The SPI port then transmits and receives 8-bit data until the data is concluded by the deassertion of SS according to the SPICON bit setting. In slave mode always an input. In SPI master mode, the SS can be used to control data transfer to a slave device ...
Page 117
... SPITx FLAGS WITH INTMOD = 0 Figure 97. SPI Timing Configurations Rev Page 117 of 128 SPITx SPIRx SPITxIRQ = 1 RECEIVE SHIFT REGISTER SPITx (EMPTY) SPIRx (FULL) STOPS TRANSFER IF TIMODE = 1 RECEIVE SHIFT REGISTER Figure 96. SPI Receive and Transmit Interrupt and Status Flags ? ? ADE7518 2 C SPIRxIRQ = 1 SPIRxOF = 1 ...
Page 118
... ADE7518 2 I C-COMPATIBLE INTERFACE The ADE7518 supports a fully licensed I interface is implemented as a full hardware master. SDATA is the data I/O pin, and SCLK is the serial clock. These two pins are shared with the MOSI and SCLK pins of the on-chip SPI interface. Therefore, the user can enable only one interface on these pins at any given time ...
Page 119
... Rev Page 119 of 128 2 C communication is stopped after this event ACK BY MASTER FRAME DATA BYTE N FROM SLAVE ACK BY STOP BY SLAVE MASTER FRAME Receive Buffer SFR (SPI2CRx, 0x9B) ADE7518 9 NACK BY STOP BY MASTER MASTER . ...
Page 120
... ADE7518 RECEIVE AND TRANSMIT FIFOS 2 The I C peripheral has a 4-byte receive FIFO and a 4-byte transmit FIFO. The buffers reduce the overhead associated with using 2 the I C peripheral. Figure 100 shows the operation of the I receive and transmit FIFOs. The Tx FIFO can be loaded with four bytes to be transmitted to the slave at the beginning of a write operation ...
Page 121
... I/O PORTS PARALLEL I/O The ADE7518 uses three input/output ports to exchange data with external devices. In addition to performing general-purpose I/O, some are capable of driving an LCD or performing alternate functions for the peripherals available on-chip. In general, when a peripheral is enabled, the pins associated with it cannot be used as a general-purpose I/O. The I/O port can be configured through the SFRs listed in Table 136 ...
Page 122
... ADE7518 I/O REGISTERS Table 137. Extended Port Configuration SFR (EPCFG, 0x9F) Bit Mnemonic 7 MOD38_FP21 6 MOD38_FP22 5 MOD38_FP23 4 MOD38_TxD 3 MOD38_CF1 2 MOD38_SSb 1 MOD38_MISO 0 MOD38_CF2 Table 138. Port 0 Weak Pull-Up Enable SFR (PINMAP0, 0xB2) Bit Mnemonic 7 PINMAP0.7 6 PINMAP0.6 5 PINMAP0.5 4 PINMAP0.4 3 PINMAP0.3 2 PINMAP0.2 1 PINMAP0.1 0 PINMAP0.0 Table 139. Port 1 Weak Pull-Up Enable SFR (PINMAP1, 0xB3) ...
Page 123
... This bit reflects the state of the SDEN/P2.3 pin. It can be written only. 1 This bit reflects the state of the P2.2/FP16 pin. It can be written or read. 1 This bit reflects the state of the P2.1/FP17 pin. It can be written or read. 1 This bit reflects the state of the P2.0/FP18 pin. It can be written or read. Rev Page 123 of 128 ADE7518 ...
Page 124
... ADE7518 Table 144. Port 0 Alternate Functions Pin No. Alternate Function P0.0 BCTRL External Battery Control Input INT1 External Interrupt INT1 Wake-up from PSM2 Operating Mode P0.1 FP19 LCD Segment Pin P0.2 CF1 ADE Calibration Frequency Output P0.3 CF2 ADE Calibration Frequency Output P0.4 MOSI SPI Data Line ...
Page 125
... The weak internal pull-up is disabled by writing PINMAP2.x. Port 2 pins also have various secondary functions as described in Table 146. The alternate functions of Port 2 pins can be activated only if the corresponding bit latch in the Port 2 SFR contains a 1. Otherwise, the port pin remains at 0. Rev Page 125 of 128 ADE7518 ...
Page 126
... ADE7518 DETERMINING THE VERSION OF THE ADE7518 The ADE7518 holds in its internal flash registers a value that defines its version. This value helps to determine if users have the latest version of the part. The ADE7518 version corresponding to this data sheet is ADE7518V3.4. To access this value, the following procedure can be followed: 1 ...
Page 127
... No Yes 8 −40°C to +85°C No Yes 16 −40°C to +85°C No Yes 16 −40°C to +85°C Rev Page 127 of 128 12.20 12.00 SQ 11. 10.20 TOP VIEW 10.00 SQ (PINS DOWN) 9. 0.27 0.22 0.17 Package Description 64-Lead LQFP 64-Lead LQFP, Reel 64-Lead LQFP 64-Lead LQFP, Reel ADE7518 Package Option ST-64-2 ST-64-2 ST-64-2 ST-64-2 ...
Page 128
... ADE7518 NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...