ade7518 Analog Devices, Inc., ade7518 Datasheet - Page 38

• Manufacturer Part Number: ade7518
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc, And Lcd Driver
• Manufacturer: Analog Devices, Inc.

ADE7518
Table 35. ACCMODE Register (0x0F)
Bit
7 to 6
5
4
3
2
1
0
Table 36. GAIN Register (0x1B)
Bit
7 to 5
4
3
2 to 0
INTERRUPT STATUS/ENABLE SFRS
Table 37. Interrupt Status 1 SFR (MIRQSTL, 0xDC)
Bit
7
6
5
4
3
2
1
0
Mnemonic
Reserved
VARSIGN
APSIGN
ABSVARM
SAVARM
POAM
ABSAM
Mnemonic
PGA2[2:0]
Reserved
CFSIGN_OPT
PGA1[2:0]
Interrupt Flag
ADEIRQFLAG
Reserved
Reserved
VARSIGN
APSIGN
VANOLOAD
RNOLOAD
APNOLOAD
Default
0
0
0
0
0
0
0
Default
000
0
0
000
Description
This bit is set if any of the ADE status flags that are enabled to generate an ADE interrupt are set. This bit is
automatically cleared when all of the enabled ADE status flags are cleared.
Reserved.
Reserved.
Logic 1 indicates that the reactive power sign has changed according to the configuration of the ACCMODE register.
Logic 1 indicates that the active power sign has changed according to the configuration of the ACCMODE register.
Logic 1 indicates that an interrupt has been caused by an apparent power no load detection. This interrupt is
also used to reflect the part entering the I
Logic 1 indicates that an interrupt has been caused by a reactive power no load detection.
Logic 1 indicates that an interrupt has been caused by an active power no load detection.
Description
Configuration bit to select the event that triggers a reactive power sign interrupt. If set to 0, VARSIGN
interrupt occurs when reactive power changes from positive to negative. If this bit is set to 1, VARSIGN
interrupt occurs when reactive power changes from negative to positive.
Configuration bit to select event that triggers an active power sign interrupt. If set to 0, APSIGN
interrupt occurs when active power changes from positive to negative. If this bit is set to 1, APSIGN
interrupt occurs when active power changes from negative to positive.
Logic 1 enables absolute value accumulation of reactive power in energy register and pulse output.
Logic 1 enables reactive power accumulation depending on the sign of the active power. If active
power is positive, VAR is accumulated as it is. If active power is negative, the sign of the VAR is
reversed for the accumulation. This accumulation mode affects both the VAR registers (VARHR,
RVARHR, LVARHR) and the pulse output when connected to VAR.
Logic 1 enables positive-only accumulation of active power in the WATTHR energy register and
pulse output.
Logic 1 enables absolute value accumulation of active power in the WATTHR energy register and
pulse output.
Description
These bits define the voltage channel input gain.
PGA2[2:0]
000
001
010
011
100
Reserved.
This bit defines where the CF change of sign detection (APSIGN or VARSIGN) is implemented.
CFSIGN_OPT
0
1
These bits define the current channel input gain.
PGA1[2:0]
000
001
010
011
100
These bits should be left at their default value for proper operation.
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rms
no load mode.
Result
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Result
Filtered power signal
On a per CF pulse basis
Result
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16