ade7518 Analog Devices, Inc., ade7518 Datasheet - Page 119

• Manufacturer Part Number: ade7518
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc, And Lcd Driver
• Manufacturer: Analog Devices, Inc.

Table 135. I
Bit
7
6
5
4
3 to 2
1
0
READ AND WRITE OPERATIONS
Figure 98 and Figure 99 depict I
respectively. Note that the LSB of the I2CADR register is used to
select whether a read or write operation is performed on the
slave device. During the read operation, the master acknowledges
are generated automatically by the I
generated NACK (no acknowledge) before the end of a read
operation is also automatically generated after the I2CRCT,
Bits[4:0] have been read from the slave. If the I2CADR register
is updated during a transmission, instead of generating a stop at
the end of the read or write operation, the master generates a
start condition and continues with the next communication.
SDATA
SCLK
START BY
MASTER
Mnemonic
I2CBUSY
I2CNOACK
I2CRxIRQ
I2CTxIRQ
I2CFIFOSTAT[1:0]
I2CACC_ERR
I2CTxWR_ERR
2
C Interrupt Status Register SFR (SPI2CSTAT, 0xEA)
A6
1
SERIAL BUS ADDRESS BYTE
A5
SDATA
SCLK
A4
START BY
MASTER
FRAME 1
A3
Default
0
0
0
0
00
0
0
A2
A6
1
2
C read and write operations,
A1
SERIAL BUS ADDRESS BYTE
A5
2
C peripheral. The master-
A0
A4
Description
This bit is set to Logic 1 when the I
I
does not send an acknowledgement. The I
Write a 0 to this bit to clear it.
I
Write a 0 to this bit to clear it.
I
Write a 0 to this bit to clear it.
Status Bits for 3- or 4-Byte Deep I
used in I
I2CFIFOSTAT[1:0]
00
01
10
11
Set when trying to write and read at the same time. Write a 0 to this bit to clear it.
Set when write was attempted when I
2
2
2
C No Acknowledgement Transmit Interrupt. This bit is set to Logic 1 when the slave device
C Receive Interrupt. This bit is set to Logic 1 when the receive FIFO is not empty.
C Transmit Interrupt. This bit is set to Logic 1 when the transmit FIFO is empty.
R/W
FRAME 1
ACK BY
SLAVE
A3
9
A2
2
C communication (receive or transmit) because only one FIFO is active at a time.
D7
1
A1
D6
DATA BYTE 1 FROM MASTER
Figure 98. I
A0
Figure 99. I
D5
Rev. 0 | Page 119 of 128
R/W
D4
ACK BY
SLAVE
FRAME 2
Result
FIFO empty
Reserved
FIFO full
FIFO half full
D3
2
2
9
C Write Operation
C Read Operation
D2
D7
1
2
C FIFO. The FIFO monitored in these two bits is the one currently
D1
D6
Reading the SPI/I
Reading the SPI2CRx SFR should be done with a 2-cycle
instruction, such as
Mov a, spi2crx or Mov R0, spi2crx
A 3-cycle instruction such as
Mov 3dh, spi2crx
does not transfer the right data into RAM Address 0x3D.
2
C interface is used. When this bit is set, the Tx FIFO is emptied.
DATA BYTE 1 FROM MASTER
2
D0
D5
C transmit FIFO was full. Write a 0 to this bit to clear it.
ACK BY
MASTER
2
9
D4
C communication is stopped after this event.
FRAME 2
D3
D7
D2
1
2
C Receive Buffer SFR (SPI2CRx, 0x9B)
D6
D1
DATA BYTE N FROM SLAVE
D5
D0
ACK BY
SLAVE
D4
FRAME N + 1
9
D3
STOP BY
MASTER
D2
D1
D0
NACK BY
MASTER
9
.
ADE7518
STOP BY
MASTER