ade7518 Analog Devices, Inc., ade7518 Datasheet - Page 110

• Manufacturer Part Number: ade7518
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc, And Lcd Driver
• Manufacturer: Analog Devices, Inc.

ADE7518
TCLK puts Timer 2 into its baud rate generator mode, as shown
in Figure 92.
In this case, the baud rate is given by the following formula:
UART Timer Generated Baud Rates
The high integer dividers in a UART block mean that high speed
baud rates are not always possible. In addition, generating baud
rates requires the exclusive use of a timer, rendering it unusable
for other applications when the UART is required. To address
this problem, each ADE7518 has a dedicated baud rate timer
(UART timer) specifically for generating highly accurate baud
rates. The UART timer can be used instead of Timer 1 or Timer 2
for generating very accurate high speed UART baud rates,
including 115,200 bps. This timer also allows a much wider
range of baud rates to be obtained. In fact, every desired bit rate
from 12 bps to 393,216 bps can be generated to within an error
of ±0.8%. The UART timer also frees up the other three timers,
allowing them to be used for different applications. A block
diagram of the UART timer is shown in Figure 91.
Mode 1 or Mode 3 Baud Rate =
(
16
×
[
65536
TRANSITION
−
T2EX
DETECTOR
PIN
PIN
(
f
T2
NOTE: AVAILABILITY OF ADDITIONAL
EXTERNAL INTERRUPT
RCAP
CORE
f
CORE
2
H
:
RCAP
C/ T2 = 0
C/ T2 = 1
2
L
)
EXEN2
]
)
CONTROL
CONTROL
TR2
Figure 92. Timer 2, UART Baud Rates
EXF 2
Rev. 0 | Page 110 of 128
RCAP2L
(8 BITS)
TL2
TIMER 2
INTERRUPT
RCAP2H
(8 BITS)
TH2
Two SFRs, Enhanced Serial Baud Rate Control SFR (SBAUDT,
0x9E) and UART Timer Fractional Divider SFR (SBAUDF,
0x9D), are used to control the UART timer. SBAUDT is the
baud rate control SFR; it sets up the integer divider (DIV) and
the extended divider (SBTH) for the UART timer.
The appropriate value to write to the DIV[2:0] and SBTH[1:0]
bits can be calculated using the following formula, where f
defined in the POWCON SFR (see Table 24). Note that the DIV
value must be rounded down to the nearest integer.
FRACTIONAL
DIVIDER
RELOAD
OVERFLOW
DIV
TIMER 2
+
SBTH
÷(1 + SBAUDF/64)
÷2
Figure 91. UART Timer, UART Baud Rate
f
DIV + SBTH
÷32
CORE
1
1
=
OVERFLOW
2
log
TIMER 1
0
0
0
UART TIMER
Rx/Tx CLOCK
⎛
⎜
⎜
⎝
16
1
×
log
Rx CLOCK
TIMER 1/TIMER 2
RCLK
TCLK
Baud
f
16
16
CORE
( )
2
1
1
SMOD
Rate
Tx CLOCK
0
0
TIMER 1/TIMER 2
Rx
CLOCK
Tx
CLOCK
⎞
⎟
⎟
⎠
UARTBAUDEN
Rx CLOCK
Tx CLOCK
CORE
is