ade7518 Analog Devices, Inc., ade7518 Datasheet - Page 105

• Manufacturer Part Number: ade7518
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc, And Lcd Driver
• Manufacturer: Analog Devices, Inc.

UART SERIAL INTERFACE
The ADE7518 UART can be configured in one of four modes.
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•
•
•
Variable baud rates are defined by using an internal timer to
generate any rate between 300 baud/sec and 115,200 baud/sec.
The UART serial interface provided in the ADE7518 is a full-
duplex serial interface. It is also receive-buffered by storing the
first received byte in a receive buffer until the reception of the
second byte is complete. The physical interface to the UART is
provided via the RxD (P1.0) and TxD (P1.1) pins, whereas the
firmware interface is through the SFRs presented in Table 120.
UART REGISTERS
Table 120. Serial Port SFRs
SFR
SCON
SBUF
SBAUDT
SBAUDF
Table 121. Serial Communications Control Register SFR (SCON, 0x98)
Bit
7 to 6
5
4
3
2
1
0
Shift register with baud rate fixed at f
8-bit UART with variable baud rate
9-bit UART with baud rate fixed at f
9-bit UART with variable baud rate
Address
0x9D
0x9C
0x9B
0x9A
0x99
0x98
0x9F, 0x9E
Address
0x98
0x99
0x9E
0x9D
Mnemonic
SM0, SM1
SM2
REN
TB8
RB8
TI
RI
Bit Addressable
Yes
No
No
No
Default
00
0
0
0
0
0
0
CORE
CORE
/64 or f
/12
Description
UART Serial Mode Select Bits. These bits select the serial port operating mode.
SM[1:0]
00
01
10
11
Multiprocessor Communication Enable Bit. Enables multiprocessor communication in
Mode 2 and Mode 3, and framing error detection in Mode 1.
Serial Port Receive Enable Bit. Set by user software to enable serial port reception.
Cleared by user software to disable serial port reception.
Serial Port Transmit Bit 9. The data loaded into TB8 is the ninth data bit transmitted in
Mode 2 and Mode 3.
Serial Port Receiver Bit 9. The ninth data bit received in Mode 2 and Mode 3 is latched
into RB8. For Mode 1, the stop bit is latched into RB8.
Serial Port Transmit Interrupt Flag. Set by hardware at the end of the eighth bit in Mode 0 or
at the beginning of the stop bit in Mode 1, Mode 2, and Mode 3.
TI must be cleared by user software.
Serial Port Receive Interrupt Flag. Set by hardware at the end of the eighth bit in Mode 0 or
halfway through the stop bit in Mode 1, Mode 2, and Mode 3.
RI must be cleared by user software.
In Mode 0, SM2 should be cleared.
In Mode 1, if SM2 is set, RI is not activated if a valid stop bit was not received.
If SM2 is cleared, RI is set as soon as the byte of data is received.
In Mode 2 or Mode 3, if SM2 is set, RI is not activated if the received ninth data bit in RB8 is 0. If
SM2 is cleared, RI is set as soon as the byte of data is received.
CORE
/32
Description
Serial Communications Control Register (see Table 121).
Serial Port Buffer (see Table 122).
Enhanced Serial Baud Rate Control (see Table 123).
UART Timer Fractional Divider (see Table 124).
Result (Selected Operating Mode)
Mode 0, shift register, fixed baud rate at f
Mode 1, 8-bit UART, variable baud rate.
Mode 2, 9-bit UART, fixed baud rate at f
Mode 3, 9-bit UART, variable baud rate.
Rev. 0 | Page 105 of 128
Both the serial port receive and transmit registers are accessed
through the Serial Port Buffer SFR (SBUF, 0x99). Writing to
SBUF loads the transmit register, and reading SBUF accesses a
physically separate receive register.
An enhanced UART mode is offered by using the UART timer
and by providing enhanced frame error, break error, and overwrite
error detection. This mode is enabled by setting the EXTEN bit
in the Configuration SFR (CFG, 0xAF) (see the UART Additional
Features section). The Enhanced Serial Baud Rate Control SFR
(SBAUDT, 0x9E) and UART Timer Fractional Divider SFR
(SBAUDF, 0x9D) are used to configure the UART timer and to
indicate the enhanced UART errors.
CORE
CORE
/32 or f
/12.
CORE
/16.
ADE7518