ade7518 Analog Devices, Inc., ade7518 Datasheet - Page 74

• Manufacturer Part Number: ade7518
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc, And Lcd Driver
• Manufacturer: Analog Devices, Inc.

ADE7518
INTERRUPT SYSTEM
The unique power management architecture of the ADE7518
includes an operating mode (PSM2) where the 8052 MCU core
is shut down. Events can be configured to wake the 8052 MCU
core from the PSM2 operating mode. A distinction is drawn
here between events that can trigger the wake-up of the 8052
MCU core and events that can trigger an interrupt when the
MCU core is active. Events that can wake the core are referred
to as wake-up events, whereas events that can interrupt the
program flow when the MCU is active are called interrupts.
See the 3.3 V Peripherals and Wake-Up Events section to learn
more about events that can wake the 8052 core from PSM2.
The ADE7518 provides 12 interrupt sources with three priority
levels. The power management interrupt is at the highest priority
level. The other two priority levels are configurable through the
Interrupt Priority SFR (IP, 0xB8) and the Interrupt Enable and
Priority 2 SFR (IEIP2, 0xA9).
STANDARD 8052 INTERRUPT ARCHITECTURE
The 8052 standard interrupt architecture includes two tiers of
interrupts, where some interrupts are assigned a high priority
and others are assigned a low priority.
A Priority 1 interrupt can interrupt the service routine of a
Priority 0 interrupt, and if two interrupts of different priorities
Table 57. Interrupt SFRs
SFR
IE
IP
IEIP2
WDCON
Table 58. Interrupt Enable SFR (IE, 0xA8)
Bit
7
6
5
4
3
2
1
0
Address
0xA8
0xB8
0xA9
0xC0
Address
0xAF
0xAE
0xAD
0xAC
0xAB
0xAA
0xA9
0xA8
Figure 73. Standard 8052 Interrupt Priority Levels
HIGH
LOW
Default
0x00
0x00
0xA0
0x10
Mnemonic
EA
Reserved
ET2
ES
ET1
EX1
ET0
EX0
PRIORITY 1
PRIORITY 0
Description
Enables All Interrupt Sources. Set by the user. Cleared by the user to disable all interrupt sources.
This bit should be left cleared for proper operation.
Enables the Timer 2 Interrupt. Set by the user.
Enables the UART Serial Port Interrupt. Set by the user.
Enables the Timer 1 Interrupt. Set by the user.
Enables the External Interrupt 1 (INT1). Set by the user.
Enables the Timer 0 Interrupt. Set by the user.
Enables External Interrupt 0 (INT0). Set by the user.
Bit Addressable
Yes
Yes
No
Yes
Description
Interrupt Enable (see Table 58).
Interrupt Priority (see Table 59).
Interrupt Enable and Priority 2 (see Table 60).
Watchdog Timer (see Table 65 and the Writing to the Watchdog Timer SFR
(WDCON, 0xC0) section).
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occur at the same time, the Priority 1 interrupt is serviced first.
An interrupt cannot be interrupted by another interrupt of the
same priority level. If two interrupts of the same priority level
occur simultaneously, a polling sequence is observed (see the
Interrupt Priority section).
INTERRUPT ARCHITECTURE
The ADE7518 possesses advanced power supply managment
features. To ensure a fast response to time-critical power supply
issues, such as a loss of line power, the power supply managment
interrupt should be able to interrupt any interrupt service routine.
To enable the user to have full use of the standard 8052 interrupt
priority levels, an additional priority level is added for the power
supply management (PSM) interrupt. The PSM interrupt is the
only interrupt at this highest interrupt priority level.
See the Power Supply Management (PSM) Interrupt section for
more information on the PSM interrupt.
INTERRUPT REGISTERS
The control and configuration of the interrupt system is carried
out through four interrupt-related SFRs discussed in this section.
Figure 74. Interrupt Architecture
HIGH
LOW
PRIORITY 1
PRIORITY 0
PSM