ade7518 Analog Devices, Inc., ade7518 Datasheet - Page 112

• Manufacturer Part Number: ade7518
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc, And Lcd Driver
• Manufacturer: Analog Devices, Inc.

ADE7518
SERIAL PERIPHERAL INTERFACE (SPI)
The ADE7518 integrates a complete hardware serial peripheral
interface on-chip. The SPI is full duplex so that eight bits of data
are synchronously transmitted and simultaneously received.
This SPI implementation is double buffered, allowing users to
read the last byte of received data while a new byte is shifted in.
The next byte to be transmitted can be loaded while the current
byte is shifted out.
The SPI port can be configured for master or slave operation. The
physical interface to the SPI is via the MISO (P0.5), MOSI (P0.4),
SPI REGISTERS
Table 126. SPI SFR List
SFR Address
0x9A
0x9B
0xE8
0xE9
0xEA
Table 127. SPI/I
Bit
7 to 0
Table 128. SPI/I
Bit
7 to 0
Mnemonic
SPI2CTx
Mnemonic
SPI2CRx
2
2
C Transmit Buffer SFR (SPI2CTx, 0x9A)
C Receive Buffer SFR (SPI2CRx, 0x9B)
Name
SPI2CTx
SPI2CRx
SPIMOD1
SPIMOD2
SPISTAT
Default
0
Default
0
R/W
W
R
R/W
R/W
R/W
Description
SPI or I
input. When a write is requested, the FIFO output is sent on the SPI or I
Description
SPI or I
transferred to the SPI2CRx SFR. A new data byte from the SPI or I
2
2
C Transmit Buffer. When SPI2CTx SFR is written, its content is transferred to the transmit FIFO
C Receive Buffer. When SPI2CRx SFR is read, one byte from the receive FIFO output is
Length (Bits)
8
8
8
8
8
Rev. 0 | Page 112 of 128
Default
0
0
0x10
0
0
SCLK (P0.6), and SS (P0.7) pins, whereas the firmware interface
is via the SPI Configuration SFR 1 (SPIMOD1, 0xE8), the SPI
Configuration SFR 2 (SPIMOD2, 0xE9), the SPI Interrupt
Status SFR (SPISTAT, 0xEA), the SPI/I
(SPI2CTx, 0x9A), and the SPI/I
(SPI2CRx, 0x9B).
Note that the SPI pins are shared with the I
user can enable only one interface at a time. The SCPS bit in the
Configuration SFR (CFG, 0xAF) selects which peripheral is active.
Description
SPI/I
SPI/I
SPI Configuration SFR 1 (see Table 129).
SPI Configuration SFR 2 (see Table 130).
SPI Interrupt Status (see Table 131).
2
2
C Transmit Buffer (see Table 127).
C Receive Buffer (see Table 128).
2
C bus is written to the FIFO input.
2
C Receive Buffer SFR
2
C bus.
2
C Transmit Buffer SFR
2
C pins. Therefore, the