ade7518 Analog Devices, Inc., ade7518 Datasheet - Page 41

• Manufacturer Part Number: ade7518
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc, And Lcd Driver
• Manufacturer: Analog Devices, Inc.

ANALOG-TO-DIGITAL CONVERSION
Each ADE7518 has two Σ-Δ analog-to-digital converters
(ADCs). The outputs of these ADCs are mapped directly to
waveform sampling SFRs (Address 0xE2 to Address 0xE7) and
are used for energy measurement internal digital signal processing.
In PSM1 (battery mode) and PSM2 (sleep mode), the ADCs are
powered down to minimize power consumption.
For simplicity, the block diagram in Figure 38 shows a first-
order Σ -Δ ADC. The converter is made up of the Σ -Δ modulator
and the digital low-pass filter.
A Σ -Δ modulator converts the input signal into a continuous serial
stream of 1s and 0s at a rate determined by the sampling clock.
In the ADE7518, the sampling clock is equal to 4.096 MHz/5.
The 1-bit DAC in the feedback loop is driven by the serial data
stream. The DAC output is subtracted from the input signal.
If the loop gain is high enough, the average value of the DAC
output (and, therefore, the bit stream) can approach that of the
input signal level.
For any given input value in a single sampling interval, the data
from the 1-bit ADC is virtually meaningless. A meaningful
result is obtained only when a large number of samples is
averaged. This averaging is carried into the second part of the
ADC, the digital low-pass filter. By averaging a large number of
bits from the modulator, the low-pass filter can produce 24-bit
data-words that are proportional to the input signal level.
The Σ -Δ converter uses two techniques to achieve high resolution
from what is essentially a 1-bit conversion technique. The first
is oversampling. Oversampling means that the signal is sampled
at a rate (frequency) that is many times higher than the bandwidth
of interest. For example, the sampling rate in the ADE7518 is
4.096 MHz/5, or 819.2 kHz, and the band of interest is 40 Hz to
2 kHz. Oversampling has the effect of spreading the quantization
LOW-PASS FILTER
ANALOG
R
C
+
–
Figure 38. First-Order
INTEGRATOR
Rev. 0 | Page 41 of 128
V
REF
1-BIT DAC
MCLK/5
noise (noise due to sampling) over a wider bandwidth. With the
noise spread more thinly over a wider bandwidth, the quantization
noise in the band of interest is lowered (see Figure 37).
However, oversampling alone is not efficient enough to improve
the signal-to-noise ratio (SNR) in the band of interest. For example,
an oversampling ratio of four is required to increase the SNR by
only 6 dB (1 bit). To keep the oversampling ratio at a reasonable
level, it is possible to shape the quantization noise so that the
majority of the noise lies at the higher frequencies. In the Σ -Δ
modulator, the noise is shaped by the integrator, which has a
high-pass-type response for the quantization noise. The result is
that most of the noise is at the higher frequencies, where it can
be removed by the digital low-pass filter. This noise shaping is
shown in Figure 37.
SIGNAL
SIGNAL
... 10100101 ...
Σ
-∆ ADC
COMPARATOR
NOISE
NOISE
LATCHED
0
0
Figure 37. Noise Reduction Due to Oversampling and
OUTPUT FROM DIGITAL
2
2
Noise Shaping in the Analog Modulator
HIGH RESOLUTION
DIGITAL
FILTER
LPF
LOW-PASS
DIGITAL
FILTER
FREQUENCY (kHz)
FREQUENCY (kHz)
FILTER (RC)
ANTIALIAS
409.6
409.6
24
SHAPED
NOISE
FREQUENCY
SAMPLING
ADE7518
819.2
819.2