dsp56824 Freescale Semiconductor, Inc, dsp56824 Datasheet - Page 60

• Manufacturer Part Number: dsp56824
• Description: 16-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

5.2 Electrical Design Considerations
Use the following list of considerations to assure correct DSP operation:
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Provide a low-impedance path from the board power supply to each V
the board ground to each V
The minimum bypass requirement is to place six 0.01–0.1 F capacitors positioned as close as
possible to the package supply pins, one capacitor for each of the “Circuits Supplied” groups listed
in Table 34 on page 55. The recommended bypass configuration is to place one bypass capacitor on
each of the ten V
Ensure that capacitor leads and associated printed circuit traces that connect to the chip V
V
Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for V
Bypass the V
grade capacitor such as a tantalum capacitor.
Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal.
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient currents in the V
All inputs must be terminated (i.e., not allowed to float) using CMOS levels.
Take special care to minimize noise levels on the V
When using Wired-OR mode on the SPI or the MODx/IRQx pins, the user must provide an external
pull-up device.
Designs that utilize the TRST/DE pin for JTAG port or OnCE module functionality (such as
development or debugging systems) should allow a means to assert TRST whenever RESET is
asserted, as well as a means to assert TRST independently of RESET. Designs that do not require
debugging functionality, such as consumer products, should tie these pins together.
Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide
an interface to this port to allow in-circuit Flash programming.
SS
(GND) pins are less than 0.5” per capacitor lead.
This device contains protective circuitry to guard against damage due to
high static voltage or electrical fields. However, normal precautions are
advised to avoid application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of operation is
enhanced if unused inputs are tied to an appropriate logic voltage level
(e.g., either GND or V
DD
and GND layers of the PCB with approximately 100 F, preferably with a high-
DD
Freescale Semiconductor, Inc.
/V
For More Information On This Product,
SS
pairs, including V
SS
(GND) pin.
CC
DSP56824 Technical Data
Go to: www.freescale.com
DD
).
and GND circuits.
WARNING:
DDPLL
/V
DDPLL
SSPLL.
and V
SSPLL
DD
pins.
pin on the DSP, and from
DD
and GND.
DD
and