dsp56824 Freescale Semiconductor, Inc, dsp56824 Datasheet - Page 31

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dsp56824

Manufacturer Part Number
dsp56824
Description
16-bit Digital Signal Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
No.
66
67
68
69
70
71
72
73
74
75
1.
70 MHz, T = 7.14 ns.
2.
cases:
3.
4.
5.
6.
Stop state. This is not the minimum required so that the IRQA interrupt is accepted.
7.
Table 26. Reset, Stop, Wait, Mode Select, and Interrupt Timing (Continued)
In the formulas, T = 1/2 the clock cycle and WS = the number of wait states. For an internal frequency of
Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two
• After power-on reset
• When recovering from Stop state
The instruction fetch is visible on the pins only in Mode 2 and Mode 3.
Timing No. 72 is for all IRQx interrupts, while timing No. 73 is only when exiting the Wait state.
Timing No. 72 triggers off T0 in the Normal state and off phi0 when exiting the Wait state.
The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the
The interrupt instruction fetch is visible on the pins only in Mode 3.
Mode and XCOLF Select Hold Time
Edge-sensitive Interrupt Request Width
IRQA, IRQB Assertion to External Data Memory Access
Out Valid, caused by first instruction execution in the
interrupt service routine
IRQA, IRQB Assertion to General Purpose Output Valid,
caused by first instruction execution in the interrupt service
routine
Synchronous setup time from IRQA, IRQB assertion to
Synchronous CLKO High
Synchronous recovery from Wait State
IRQA Width Assertion to Recover from Stop State
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
Duration for Level Sensitive IRQA Assertion to Cause the
Fetch of First IRQA Interrupt Instruction (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
Delay from Level Sensitive IRQA Assertion to First Interrupt
Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
CLKO Low to First Interrupt Vector Address Out Valid after
2
Freescale Semiconductor, Inc.
Characteristics
For More Information On This Product,
4, 5
DSP56824 Technical Data
Go to: www.freescale.com
6
2
Reset, Stop, Wait, Mode Select, and Interrupt Timing
7
2
524,336T + 2.
31T + 3.7
24T + 4.4
524,329T
524,329T
22T + 2.5
28 + 2.5
2T + 3.8
2T + 3.8
Min
22T
22T
1.9
0
5
1
70 MHz
Max
2T
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
31

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