dsp56824 Freescale Semiconductor, Inc, dsp56824 Datasheet - Page 12

• Manufacturer Part Number: dsp56824
• Description: 16-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

2.5 Interrupt and Mode Control Signals
12
MODA
IRQA
MODB
IRQB
RESET
Signal
Name
Signal
Type
Input
Input
Input
Input
Input
During
Table 10. Interrupt and Mode Control Signals
Reset
State
Input
Input
Input
Freescale Semiconductor, Inc.
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Mode Select A—During hardware reset, MODA and MODB select one of the
four initial chip operating modes latched into the Operating Mode Register
(OMR). Several clock cycles (depending on PLL setup time) after leaving the
Reset state, the MODA pin changes to external interrupt request IRQA. The
chip operating mode can be changed by software after reset.
External Interrupt Request A—The IRQA input is a synchronized external
interrupt request that indicates that an external device is requesting service. It
can be programmed to be level-sensitive or negative-edge-triggered. If level-
sensitive triggering is selected, an external pull up resistor is required for wired-
OR operation.
If the processor is in the Stop state and IRQA is asserted, the processor will exit
the Stop state.
Mode Select B/External Interrupt Request B—During hardware reset, MODA
and MODB select one of the four initial chip operating modes latched into the
Operating Mode Register (OMR). Several clock cycles (depending on PLL setup
time) after leaving the Reset state, the MODB pin changes to external interrupt
request IRQB. After reset, the chip operating mode can be changed by
software.
External Interrupt Request B—The IRQB input is an external interrupt request
that indicates that an external device is requesting service. It can be
programmed to be level-sensitive or negative-edge-triggered. If level-sensitive
triggering is selected, an external pull up resistor is required for wired-OR
operation.
Reset—This input is a direct hardware reset on the processor. When RESET is
asserted low, the DSP is initialized and placed in the Reset state. A Schmitt
trigger input is used for noise immunity. When the RESET pin is deasserted, the
initial chip operating mode is latched from the MODA and MODB pins. The
internal reset signal should be deasserted synchronous with the internal clocks.
To ensure complete hardware reset, RESET and TRST/DE should be asserted
together. The only exception occurs in a debugging environment when a
hardware DSP reset is required and it is necessary not to reset the OnCE/JTAG
module. In this case, assert RESET, but do not assert TRST/DE.
DSP56824 Technical Data
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Signal Description