dsp56824 Freescale Semiconductor, Inc, dsp56824 Datasheet - Page 14

• Manufacturer Part Number: dsp56824
• Description: 16-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

2.7 Serial Peripheral Interface (SPI) Signals
14
MISO0
PC0
MOSI0
PC1
SCK0
PC2
SS0
PC3
Signal
Name
Table 13. Serial Peripheral Interface (SPI0 and SPI1) Signals
Input or
Input or
Input or
Input or
Signal
Output
Output
Output
Output
Output
Output
Output
Input/
Input/
Input/
Type
Input
During
Reset
State
Freescale Semiconductor, Inc.
Input
Input
Input
Input
For More Information On This Product,
SPI0 Master In/Slave Out (MISO0)—This serial data pin is an input to a
master device and an output from a slave device. The MISO0 line of a slave
device is placed in the high-impedance state if the slave device is not
selected. The driver on this pin can be configured as an open-drain driver
by the SPI’s WOM bit when this pin is configured for SPI operation. When
using Wired-OR mode, the user must provide an external pull-up device.
Port C GPIO 0 (PC0)—This pin is a GPIO pin called PC0 when the SPI
MISO0 function is not being used.
After reset, the default state is GPIO input.
SPI0 Master Out/Slave In (MOSI0)—This serial data pin is an output from
a master device and an input to a slave device. The master device places
data on the MOSI0 line a half-cycle before the clock edge that the slave
device uses to latch the data. The driver on this pin can be configured as an
open-drain driver by the SPI’s WOM bit when this pin is configured for SPI
operation. When using Wired-OR mode, the user must provide an external
pull-up device.
Port C GPIO 1 (PC1)—This pin is a GPIO pin called PC1 when the SPI
MOSI0 function is not being used.
After reset, the default state is GPIO input.
SPI0 Serial Clock—This bidirectional pin provides a serial bit rate clock for
the SPI. This gated clock signal is an input to a slave device and is
generated as an output by a master device. Slave devices ignore the SCK
signal unless the slave select pin is active low. In both master and slave SPI
devices, data is shifted on one edge of the SCK signal and is sampled on
the opposite edge where data is stable. The driver on this pin can be
configured as an open-drain driver by the SPI’s WOM bit when this pin is
configured for SPI operation. When using Wired-OR mode, the user must
provide an external pull-up device.
Port C GPIO 2 (PC2)—This pin is a GPIO pin called PC2 when the SPI
SCK0 function is not being used.
After reset, the default state is GPIO input.
SPI0 Slave Select—This input pin selects a slave device before a master
device can exchange data with the slave device. SS must be low before
data transactions and must stay low for the duration of the transaction. The
SS line of the master must be held high.
Port C GPIO 3 (PC3)—This pin is a GPIO pin called PC3 when the SPI
SS0 function is not being used.
After reset, the default state is GPIO input.
DSP56824 Technical Data
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Signal Description