dsp56824 Freescale Semiconductor, Inc, dsp56824 Datasheet - Page 26

• Manufacturer Part Number: dsp56824
• Description: 16-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

3.6 Port A External Bus Synchronous Timing
(V
3.6.1
The DSP56824 external bus synchronous timing specifications are designed and tested at the maximum
capacitive load of 50 pF, including stray capacitance. Typically, the drive capability of the pins A0–A15,
D0–D15, PS, DS, RD, and WR derates linearly at 1.7 ns per 20 pF of additional capacitance from 50 pF to
250 pF of loading. The CLKO pin drive capability is 20 pF. When an internal memory access follows an
external memory access, the PS, DS, RD, and WR strobes remain deasserted and A0–A15 do not change
from their previous state.
26
SS
No
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
= 0 V, V
External Input Clock High to CLKO High
CLKO High to A0–A15 Valid
CLKO High to PS, DS Valid
CLKO Low to WR Asserted Low
CLKO High to RD Asserted Low
CLKO High to D0–D15 Out Valid
CLKO High to D0–D15 Out Invalid
D0–D15 In Valid to CLKO Low (Setup)
CLKO Low to D0–D15 Invalid (Hold)
CLKO Low to WR Deasserted
CLKO Low to RD Deasserted
WR Hold Time from CLKO Low
RD Hold Time from CLKO Low
CLKO High to D0–D15 Out Active
CLKO High to D0–D15 Out Tri-state
CLKO High to A0–A15 Invalid
CLKO High to PS, DS Invalid
Capacitance Derating
XCO Asserted High
XCO Asserted Low
DD
In Figure 10 and Figure 11, T
phases and T
= 2.7–3.6 V, T
Table 24. External Bus Synchronous Timing
Freescale Semiconductor, Inc.
W
For More Information On This Product,
refers to wait state.
A
= –40 to +85 C, C
Characteristic
DSP56824 Technical Data
Go to: www.freescale.com
0
, T
NOTE:
1
, T
L
2
, and T
= 50 pF)
3
refer to the internal clock
–1.3
–0.9
–0.7
Min
3.4
9.0
0.9
0.3
1.1
0.4
0.9
0.2
0.6
0.7
1.9
1.8
0.2
0.2
—
Max
13.8
18.5
–2.6
–1.7
2.0
3.1
6.4
4.8
3.1
0.3
0.6
0.3
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns