dsp56824 Freescale Semiconductor, Inc, dsp56824 Datasheet - Page 11

• Manufacturer Part Number: dsp56824
• Description: 16-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

D0–D15
Signal
Signal
Name
Name
WR
DS
RD
PS
Signal
Output
Output
Output
Output
l Type
Signa
Outpu
Input/
Type
t
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Tri-stated
During
During
Reset
Reset
State
State
Freescale Semiconductor, Inc.
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Table 9. Bus Control Signals
Data Bus—Read data is sampled in by the trailing edge of T2, while write data
output is enabled by the leading edge of T2 and tri-stated by the leading edge of
T0. D0–D15 are tri-stated when the external bus is inactive.
Program Memory Select—PS is asserted low for external program memory
access. If the external bus is not used during an instruction cycle (T0, T1, T2,
T3), PS goes high in T0.
Data Memory Select—DS is asserted low for external data memory access. If
the external bus is not used during an instruction cycle (T0, T1, T2, T3), DS
goes high in T0.
Write Enable—WR is asserted during external memory write cycles. When
WR is asserted low in T1, pins D0–D15 become outputs and the DSP puts
data on the bus during the leading edge of T2. When WR is deasserted high in
T3, the external data is latched inside the external device. When WR is
asserted, it qualifies the A0–A15, PS, and DS pins. WR can be connected
directly to the WE pin of a Static RAM.
Read Enable—RD is asserted during external memory read cycles. When RD
is asserted low late T0/early T1, pins D0–D15 become inputs and an external
device is enabled onto the DSP data bus. When RD is deasserted high in T3,
the external data is latched inside the DSP. When RD is asserted, it qualifies
the A0–A15, PS, and DS pins. RD can be connected directly to the OE pin of a
Static RAM or ROM.
Table 8. Data Bus Signals
DSP56824 Technical Data
Go to: www.freescale.com
Signal Description
Signal Description
Address, Data, and Bus Control Signals
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