dsp56824 Freescale Semiconductor, Inc, dsp56824 Datasheet - Page 18

• Manufacturer Part Number: dsp56824
• Description: 16-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

2.10 JTAG/OnCE™ Port Signals
18
TCK
TMS
TDI
TDO
TRST
DE
Signal
Name
Signal
Output
Output
Type
Input
Input
Input
Input
Table 16. JTAG/On-Chip Emulation (OnCE) Signals
pulled high
pulled high
pulled high
pulled low
Tri-stated Test Data Output—This tri-statable output pin provides a serial output data
internally
internally
internally
internally
During
Reset
State
Input,
Input,
Input,
Input,
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Test Clock Input—This input pin provides a gated clock to synchronize the test
logic and shift serial data to the JTAG/OnCE port. The pin is connected
internally to a pull-down resistor.
controller’s state machine. It is sampled on the rising edge of TCK and has an
on-chip pull-up resistor.
Test Data Input—This input pin provides a serial input data stream to the
JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip
pull-up resistor.
stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR
controller states, and changes on the falling edge of TCK.
Test Reset—As an input, a low signal on this pin provides a reset signal to the
JTAG TAP controller.
Debug Event—When programmed within the OnCE port as an output, DE
provides a low pulse on recognized debug events; when configured as an
output signal, the TRST input is disabled.
To ensure complete hardware reset, TRST/DE should be asserted whenever
RESET is asserted. The only exception occurs in a debugging environment
when a hardware DSP reset is required and it is necessary not to reset the
OnCE/JTAG module. In this case, assert RESET, but do not assert TRST/DE.
This pin is connected internally to a pull-up resistor.
Test Mode Select Input—This input pin is used to sequence the JTAG TAP
DSP56824 Technical Data
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Signal Description