dsp56824 Freescale Semiconductor, Inc, dsp56824 Datasheet - Page 10

• Manufacturer Part Number: dsp56824
• Description: 16-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

2.3 Clock and Phase Lock Loop Signals
2.4 Address, Data, and Bus Control Signals
10
V
V
EXTAL
Signal
(number of pins)
Name
CLKO
SXFC
XTAL
A0–A15
SS
SSPLL
Signal
Name
Signal Name
(9)
Signal
Output
Output
Type
Input
Input
Signal
Output
Type
During
GND—These pins provide grounding for the internal structures of the chip, and should all be
attached to V
PLL Ground—This pin supplies a quiet ground to the VCO to provide greater frequency
stability.
Reset
driven
driven
State
Chip-
Chip-
Input
Input
Tri-stated
During
Reset
State
Freescale Semiconductor, Inc.
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External Clock/Crystal Input—This input should be connected to an external
clock or oscillator. After being squared, the input clock can be selected to provide
the clock directly to the DSP core. The minimum instruction time is two input clock
periods, broken up into four phases named T0, T1, T2, and T3. This input clock
can also be selected as input clock for the on-chip PLL.
Crystal Output—This output connects the internal crystal oscillator output to an
external crystal. If an external clock is used, XTAL should not be connected.
Clock Output—This pin outputs a buffered clock signal. By programming the
CS[1:0] bits in the PLL Control Register (PCR1), the user can select between
outputting a squared version of the signal applied to EXTAL and a version of the
DSP master clock at the output of the PLL. The clock frequency on this pin can
also be disabled by programming the CS[1:0] bits in PCR1.
External Filter Capacitor—This pin is used to add an external filter circuit to the
Phase Lock Loop (PLL). Refer to Figure 9 on page 25.
Table 6. PLL and Clock Signals
SS.
Table 7. Address Bus Signals
Address Bus—A0–A15 change in T0, and specify the address for external
program or data memory accesses.
DSP56824 Technical Data
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Table 5. Grounds
Signal Description
Signal Description
Signal Description