adsp-21483 Analog Devices, Inc., adsp-21483 Datasheet - Page 52

• Manufacturer Part Number: adsp-21483
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21483/21486/21487/21488/21489
Media Local Bus
All the numbers given are applicable for all speed modes
(1024Fs, 512Fs and 256Fs for 3-pin; 512Fs and 256Fs for 5-pin)
unless otherwise specified. Please refer to the MediaLB specifi-
cation document rev 3.0 for more details.
Table 46. MLB Interface, 3-pin Specifications
1
2
Parameter
Three-Pin Characteristics
t
t
t
t
t
t
t
t
t
t
t
C
Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (pp).
The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be
MLBCLK
MCKL
MCKH
MCKR
MCKF
MPWV
DSMCF
DHMCF
MCFDZ
MCDRV
MDZH
minimized while meeting the maximum capacitive load listed.
MLB
2
1
MLB Clock Period
MLBCLK Low Time
MLBCLK High Time
MLBCLK Rise Time (V
MLBCLK Fall Time (V
MLBCLK Pulse Width Variation
DAT/SIG Input Setup Time
DAT/SIG Input Hold Time
DAT/SIG Output Time to Three-state
DAT/SIG Output Data Delay From MLBCLK Rising Edge
Bus Hold Time
DAT/SIG Pin Load
1024Fs
512Fs
256Fs
1024Fs
512Fs
256Fs
1024Fs
512Fs
256Fs
1024Fs
1024Fs
1024Fs
1024Fs
1024Fs
512Fs/256Fs
512Fs/256Fs
512Fs/256
512Fs/256
512Fs/256
IH
IL
to V
to V
IL
IH
)
)
Rev. PrA | Page 52 of 66 | March 2010
Min
6.1
14
30
9.3
14
30
1
0
0
2
4
Preliminary Technical Data
Typ
20.3
40
81
Max
1
3
1
3
0.7
2.0
t
8
40
60
MCKL
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
nspp
nspp
ns
ns
ns
ns
ns
ns
pf
pf