adsp-21483 Analog Devices, Inc., adsp-21483 Datasheet - Page 42

• Manufacturer Part Number: adsp-21483
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21483/21486/21487/21488/21489
Sample Rate Converter—Serial Output Port
For the serial output port, the frame-sync is an input and it
should meet setup and hold times with regard to SCLK on the
output port. The serial data output has a hold time and delay
Table 37. ASRC, Serial Output Port
1
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
The serial clock, data and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can
SRCSFS
SRCHFS
SRCCLKW
SRCCLK
SRCTDD
SRCTDH
be either CLKIN or any of the DAI pins.
1
1
1
1
Frame Sync Setup Before Serial Clock Rising Edge
Frame Sync Hold After Serial Clock Rising Edge
Clock Width
Clock Period
Transmit Data Delay After Serial Clock Falling Edge
Transmit Data Hold After Serial Clock Falling Edge
(SERIAL CLOCK)
(FRAME SYNC)
DAI_P20–1
DAI_P20–1
DAI_P20–1
(DATA)
t
SRCTDH
Figure 28. ASRC Serial Output Port Timing
Rev. PrA | Page 42 of 66 | March 2010
t
SRCTDD
t
SRCCLKW
t
SRCSFS
SAMPLE EDGE
specification with regard to serial clock. Note that serial clock
rising edge is the sampling edge and the falling edge is the
drive edge.
t
SRCHFS
t
SRCCLK
Min
4
5.5
(t
t
1
PCLK
PCLK
× 4
× 4) ÷ 2 – 1
Preliminary Technical Data
Max
9.9
Unit
ns
ns
ns
ns
ns
ns