adsp-21483 Analog Devices, Inc., adsp-21483 Datasheet - Page 31

• Manufacturer Part Number: adsp-21483
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
SDRAM Interface Enable/Disable Timing (166 MHz SDCLK)
Table 27. SDRAM Interface Enable/Disable Timing
1
Parameter
Switching Characteristics
t
t
t
t
t
t
For f
DSDC
ENSDC
DSDCC
ENSDCC
DSDCA
ENSDCA
CCLK
= 400 MHz (core clock to SDCLK ratio = 1:2.5).
Command Disable After CLKIN Rise
Command Enable After CLKIN Rise
SDCLK Disable After CLKIN Rise
SDCLK Enable After CLKIN Rise
Address Disable After CLKIN Rise
Address Enable After CLKIN Rise
COMMAND
COMMAND
SDCLK
SDCLK
CLKIN
ADDR
ADDR
Figure 19. SDRAM Interface Enable/Disable Timing
Rev. PrA | Page 31 of 66 | March 2010
1
t
t
t
t
t
ENSDCA
ENSDCC
t
DSDCC
DSDCA
ENSDC
ADSP-21483/21486/21487/21488/21489
DSDC
Min
4.0
3.8
2 × t
PCLK
– 4
Max
2 × t
8.5
9.2
4 × t
PCLK
PCLK
+ 3
Unit
ns
ns
ns
ns
ns
ns