adsp-21483 Analog Devices, Inc., adsp-21483 Datasheet - Page 32

• Manufacturer Part Number: adsp-21483
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21483/21486/21487/21488/21489
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD,
AMI_WR, and strobe timing parameters only apply to asyn-
chronous access mode.
Table 28. Memory Read—Bus Master
1
2
3
4
5
6
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
W = (number of wait states specified in AMICTLx register) × t
HI = RHC + IC (RHC = (number of Read Hold Cycles specified in AMICTLx register) x t
IC = (number of idle cycles specified in AMICTLx register) x t
H = (number of hold cycles specified in AMICTLx register) x t
Data delay/setup: System must meet t
The falling edge of MSx, is referenced.
Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode.
Data hold: User must meet t
AMI_ACK delay/setup: User must meet t
For Read to Read: Same bank = (1 + RHC)
DAD
DRLD
SDS
HDRH
DAAK
DSAK
DRHA
DARL
RW
RWR
5 SDCLK cycles for both the same bank and different banks.
Address, Selects Delay to Data Valid
AMI_RD Low to Data Valid
Data Setup to AMI_RD High
Data Hold from AMI_RD High
AMI_ACK Delay from Address, Selects
AMI_ACK Delay from AMI_RD Low
Address Selects Hold After AMI_RD High
Address Selects to AMI_RD Low
AMI_RD Pulse Width
AMI_RD High to AMI_WR, AMI_RD Low
HDRH
in asynchronous access mode. See
DAD
DAAK
, t
×
DRLD
SDCLK if IC is not programmed. For Read to Read: Different bank = t
, or t
, or t
DSAK
SDS.
1
, for deassertion of AMI_ACK (low). For asynchronous assertion of AMI_ACK (high) user must meet t
3, 4
2
Rev. PrA | Page 32 of 66 | March 2010
4
1, 2
2, 5
Test Conditions on Page 56
6
SDCLK
SDCLK
SDCLK
).
.
.
Min
2.5
0
RHC + 0.20
t
W – 1.4
HI + t
SDCLK
– 3.3
SDCLK
– 0.8
for the calculation of hold times given capacitive and dc loads.
SDCLK
Preliminary Technical Data
RWR
. For Read to Write: 5 SDCLK cycles + (IC – 4), at least
Max
W + t
W – 3.2
t
W – 7.0
SDCLK
–9.5 + W
SDCLK
–5.12
DAAK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
or t
DSAK
.