adsp-21483 Analog Devices, Inc., adsp-21483 Datasheet - Page 10

• Manufacturer Part Number: adsp-21483
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21483/21486/21487/21488/21489
The DAI also includes eight serial ports, four precision clock
generators (PCG), a S/PDIF transceiver, four ASRCs, and an
input data port (IDP). The IDP provides an additional input
path to the SHARC core, configurable as either eight channels
of serial data, or a single 20-bit wide synchronous parallel data
acquisition port. Each data channel has its own DMA channel
that is independent from the processor’s serial ports.
Serial Ports
The ADSP-2148x features eight synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog Devices’
AD183x family of audio codecs, ADCs, and DACs. The serial
ports are made up of two data lines, a clock, and frame sync. The
data lines can be programmed to either transmit or receive and
each data line has a dedicated DMA channel.
Serial ports can support up to 16 transmit or 16 receive channels
of audio data when all eight SPORTs are enabled, or four full
duplex TDM streams of 128 channels per frame.
The serial ports operate at a maximum data rate of f
Serial port data can be automatically transferred to and from
on-chip memory/external memory via dedicated DMA chan-
nels. Each of the serial ports can work in conjunction with
another serial port to provide TDM support. One SPORT pro-
vides two transmit signals while the other SPORT provides the
two receive signals. The frame sync and clock are shared.
Serial ports operate in five modes:
Left-justified mode is a mode where in each frame sync cycle
two samples of data are transmitted/received—one sample on
the high segment of the frame sync, the other on the low seg-
ment of the frame sync. Programs have control over various
attributes of this mode.
Each of the serial ports supports the left-justified and I
cols (I
audio codecs, ADCs, and DACs such as the Analog Devices
AD183x family), with two data pins, allowing four left-justified
or I
maximum of up to 32 I
tle-endian or big-endian transmission formats and word lengths
selectable from 3 bits to 32 bits. For the left-justified and I
modes, data-word lengths are selectable between 8 bits and 32
bits. Serial ports offer selectable synchronization and transmit
modes as well as optional μ-law or A-law companding selection
on a per channel basis. Serial port clocks and frame syncs can be
internally or externally generated.
The serial ports also contain frame sync error detection logic
where the serial ports detect frame syncs that arrive early (for
example frame syncs that arrive while the transmission/recep-
tion of the previous word is occurring). All the serial ports also
share one dedicated error interrupt.
• Standard serial mode
• Multichannel (TDM) mode
• I
• Packed I
• Left-justified mode
2
S channels (using two stereo devices) per serial port, with a
2
2
S mode
S is an industry-standard interface commonly used by
2
S mode
2
S channels. The serial ports permit lit-
Rev. PrA | Page 10 of 66 | March 2010
PCLK
2
S proto-
/4.
2
S
S/PDIF-Compatible Digital Audio Receiver/Transmitter
The S/PDIF receiver/transmitter has no separate DMA chan-
nels. It receives audio data in serial format and converts it into a
biphase encoded signal. The serial data input to the
receiver/transmitter can be formatted as left justified, I
right-justified with word widths of 16, 18, 20, or 24 bits.
The serial data, clock, and frame sync inputs to the S/PDIF
receiver/transmitter are routed through the signal routing unit
(SRU). They can come from a variety of sources such as the
SPORTs, external pins, the precision clock generators (PCGs),
and are controlled by the SRU control registers.
Asynchronous Sample Rate Converter
The sample rate converter (ASRC) contains four ASRC blocks
and is the same core as that used in the AD1896 192 kHz stereo
asynchronous sample rate converter and provides up to 128 dB
SNR. The ASRC block is used to perform synchronous or asyn-
chronous sample rate conversion across independent stereo
channels, without using internal processor resources. The four
SRC blocks can also be configured to operate together to
convert multichannel audio data without phase mismatches.
Finally, the ASRC can be used to clean up audio data from jit-
tery clock sources such as the S/PDIF receiver.
Input Data Port
The IDP provides up to eight serial input channels—each with
its own clock, frame sync, and data inputs. The eight channels
are automatically multiplexed into a single 32-bit by eight-deep
FIFO. Data is always formatted as a 64-bit frame and divided
into two 32-bit words. The serial protocol is designed to receive
audio channels in I
mode. One frame sync cycle indicates one 64-bit left/right pair,
but data is sent to the FIFO as 32-bit words (that is, one-half of a
frame at a time). The processor supports 24- and 32-bit I
and 32-bit left-justified, and 24-, 20-, 18- and 16-bit right-justi-
fied formats.
Precision Clock Generators
The precision clock generators (PCG) consist of four units, each
of which generates a pair of signals (clock and frame sync)
derived from a clock input signal. The units, A B, C, and D, are
identical in functionality and operate independently of each
other. The two signals generated by each unit are normally used
as a serial bit clock/frame sync pair.
The outputs of PCG A and B can be routed through the DAI
pins and the outputs of PCG C and D can be driven on to the
DAI as well as the DPI pins.
Digital Peripheral Interface (DPI)
The digital peripheral interface provides connections to two
serial peripheral interface ports (SPI), one universal asynchro-
nous receiver-transmitter (UART), 12 flags, a 2-wire interface
(TWI), three PWM modules (PWM3–1), and two general-pur-
pose timers.
Preliminary Technical Data
2
S, left-justified sample pair, or right-justified
2
S or
2
S, 24-