adsp-21483 Analog Devices, Inc., adsp-21483 Datasheet - Page 40

• Manufacturer Part Number: adsp-21483
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21483/21486/21487/21488/21489
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table
the IDP. For details on the operation of the PDAP, see the
Table 35. Parallel Data Acquisition Port (PDAP)
1
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
Source pins of DATA are ADDR23–0 or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.
SPHOLD
HPHOLD
PDSD
PDHD
PDCLKW
PDCLK
PDHLDD
PDSTRB
1
1
35. PDAP is the parallel mode operation of Channel 0 of
1
1
DAI_P20–1/ADDR23–4
DAI_P20–1/ADDR2
(PDAP_DATA)
(PDAP_STROBE)
(PDAP_CLK)
(PDAP_HOLD)
PDAP_HOLD Setup Before PDAP_CLK Sample Edge
PDAP_HOLD Hold After PDAP_CLK Sample Edge
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge
Clock Width
Clock Period
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word
PDAP Strobe Pulse Width
DAI_P20–1
DAI_P20–1
SAMPLE EDGE
Rev. PrA | Page 40 of 66 | March 2010
t
PDCLKW
Figure 26. PDAP Timing
t
SPHOLD
t
PDSD
t
PDHLDD
PDAP chapter of the ADSP-214xx SHARC Processor Hardware
Reference. Note that the 20-bits of external PDAP data can be
provided through the ADDR23–0 pins or over the DAI pins.
t
t
t
PDHD
PDCLK
HPHOLD
t
PDSTRB
Preliminary Technical Data
Min
2.5
2.5
3.85
2.5
(t
t
2 × t
2 × t
PCLK
PCLK
× 4
PCLK
PCLK
× 4) ÷ 2 – 3
+ 3
– 1
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns