adsp-21483 Analog Devices, Inc., adsp-21483 Datasheet - Page 12

• Manufacturer Part Number: adsp-21483
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21483/21486/21487/21488/21489
Delay Line DMA
The ADSP-2148x processor provides delay line DMA function-
ality. This allows processor reads and writes to external delay
line buffers (and hence to external memory) with limited core
interaction.
Scatter/Gather DMA
The ADSP-2148x processor provides scatter/gather DMA func-
tionality. This allows processor DMA reads/writes to/from non-
contingeous memory blocks.
FFT Accelerator
FFT accelerator implements radix-2 complex/real input, com-
plex output FFT with no core intervention.
FIR Accelerator
The FIR (finite impulse response) accelerator consists of a 1024
word coefficient memory, a 1024 word deep delay line for the
data, and four MAC units. A controller manages the accelerator.
The FIR accelerator runs at the peripheral clock frequency.
IIR Accelerator
The IIR (infinite impulse response) accelerator consists of a
1440 word coefficient memory for storage of biquad coeffi-
cients, a data memory for storing the intermediate data and one
MAC unit. A controller manages the accelerator. The IIR accel-
erator runs at the peripheral clock frequency.
Watch Dog Timer
The watch dog timer is used to supervise the stability of the sys-
tem software. When used in this way, software reloads the watch
dog timer in a regular manner so that the downward counting
timer never expires. An expiring timer then indicates that sys-
tem software might be out of control.
The ADSP-2148x processors include a 32-bit watch dog timer
that can be used to implement a software watch dog function. A
software watch dog can improve system reliability by forcing the
processor to a known state through generation of a system reset,
if the timer expires before being reloaded by software. Software
initializes the count value of the timer, and then enables the
timer.
The watch dog timer resets both the core and the internal
peripherals. After an external reset, the WDT must be disabled
by default. Software must be able to determine if the watch dog
was the source of the hardware reset by interrogating a status bit
in the watch dog timer control register.
The WDT contains a software programmable Trip Counter reg-
ister that sets the number of times that the WDT can expire
before the WDTRSTO pin is continually asserted until the next
time hardware reset is applied. The trip counter is not cleared by
the WDT generated reset. This gives software the ability to
count the number of WDT generated resets using the CUR-
TRIPVAL field in the trip counter register.
SYSTEM DESIGN
The following sections provide an introduction to system design
options and power supply issues.
Rev. PrA | Page 12 of 66 | March 2010
Program Booting
The internal memory of the ADSP-2148x boots at system
power-up from an 8-bit EPROM via the external port, an SPI
master, or an SPI slave. Booting is determined by the boot con-
figuration (BOOT_CFG2–0) pins in
Table 8. Boot Mode Selection
1
The “Running Reset” feature allows a user to perform a reset of
the processor core and peripherals, but without resetting the
PLL and SDRAM controller, or performing a boot. The
functionality of the RESETOUT/RUNRSTIN pin has now been
extended to also act as the input for initiating a Running Reset.
For more information, see the ADSP-214xx SHARC Processor
Hardware Reference.
Power Supplies
The processors have separate power supply connections for the
internal (V
internal and analog supplies must meet the V
tions. The external supply must meet the V
All external supply pins must be connected to the same power
supply.
To reduce noise coupling, the PCB should use a parallel pair of
power and ground planes for V
Target Board JTAG Emulator Connector
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-2148x pro-
cessors to monitor and control the target board processor
during emulation. Analog Devices DSP Tools product line of
JTAG emulators provides emulation at full processor speed,
allowing inspection and modification of memory, registers, and
processor stacks. The processor's JTAG interface ensures that
the emulator will not affect target system loading or timing.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appro-
priate “Emulator Hardware User's Guide”.
DEVELOPMENT TOOLS
The ADSP-2148x processors are supported with a complete set
of CROSSCORE
including Analog Devices emulators and VisualDSP++
development environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-2148x processors.
BOOT_CFG2–0
000
001
010
011
1xx
The BOOT_CFG2 pin is not available on the 100-pin package.
DD_INT
1
®
Preliminary Technical Data
) and external (V
software and hardware development tools,
Booting Mode
SPI Slave Boot
SPI Master Boot
AMI User Boot (for 8-bit Flash Boot)
No boot (processor executes from
internal ROM after reset)
Reserved
DD_INT
DD_EXT
Table
and GND.
), power supplies. The
DD_EXT
8.
DD_INT
specification.
specifica-
®