adsp-21483 Analog Devices, Inc., adsp-21483 Datasheet - Page 35

• Manufacturer Part Number: adsp-21483
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Table 30. Serial Ports—External Clock
1
2
Table 31. Serial Ports—Internal Clock
1
2
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
Referenced to sample edge.
Referenced to drive edge.
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
Referenced to the sample edge.
Referenced to drive edge.
SFSE
HFSE
SDRE
HDRE
SCLKW
SCLK
DFSE
HOFSE
DDTE
HDTE
SFSI
HFSI
SDRI
HDRI
DFSI
HOFSI
DFSIR
HOFSIR
DDTI
HDTI
SCKLIW
1
1
1
1
2
2
2
1
1
2
1
1
2
2
2
2
2
2
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in either Transmit or Receive Mode)
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in either Transmit or Receive Mode)
Receive Data Setup Before SCLK
Receive Data Hold After SCLK
Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode)
Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode)
Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode)
Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode)
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
Transmit or Receive SCLK Width
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in either Transmit or Receive
Mode)
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in either Transmit or Receive
Mode)
Receive Data Setup Before Receive SCLK
Receive Data Hold After SCLK
SCLK Width
SCLK Period
Frame Sync Delay After SCLK
(Internally Generated Frame Sync in either Transmit or Receive Mode)
Frame Sync Hold After SCLK
(Internally Generated Frame Sync in either Transmit or Receive Mode)
Transmit Data Delay After Transmit SCLK
Transmit Data Hold After Transmit SCLK
Rev. PrA | Page 35 of 66 | March 2010
ADSP-21483/21486/21487/21488/21489
Serial port signals (SCLK, FS, Data Channel A, Data Channel B)
are routed to the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided below are valid at the
DAI_P20–1 pins.
Min
2.5
2.5
1.9
2.5
(t
t
2
2
PCLK
PCLK
× 4
× 4) ÷ 2 – 0.5
Min
7
2.5
7
2.5
–1.0
–1.0
–1.0
2 × t
PCLK
– 1.5
Max
10.25
7.8
Max
4
9.75
3.25
2 × t
PCLK
+ 1.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns