adsp-21483 Analog Devices, Inc., adsp-21483 Datasheet - Page 4

• Manufacturer Part Number: adsp-21483
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21483/21486/21487/21488/21489
The diagram
up the ADSP-2148x processors. The core clock domain contains
the following features.
The block diagram of the ADSP-2148x
peripheral clock domain (also known as the I/O processor)
which contains the following features:
As shown in the functional block diagram
processor uses two computational units to deliver a significant
performance increase over the previous SHARC processors on a
range of DSP algorithms. With its SIMD computational hard-
ware, the processors can perform 2.4 GFLOPS running at 400
MHz.
FAMILY CORE ARCHITECTURE
The ADSP-2148x is code compatible at the assembly level with
the ADSP-2146x, ADSP-2137x, ADSP-2136x, ADSP-2126x,
ADSP-21160, and ADSP-21161, and with the first generation
ADSP-2106x SHARC processors. The ADSP-2148x shares
architectural features with the ADSP-2126x, ADSP-2136x,
ADSP-2137x, ADSP-2146x and ADSP-2116x SIMD SHARC
processors, as shown in
sections.
• Two processing elements (PEx, PEy), each of which com-
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting 2x64-bit data
• One periodic interval timer with pinout
• On-chip SRAM (5M bit)
• On-chip mask-programmable ROM (4M bit)
• JTAG test access port for emulation and boundary scan.
• IOD0 (peripheral DMA) and IOD1 (external port DMA)
• Peripheral and external port buses for core connection
• External port with an AMI and SDRAM controller
• 4 units for PWM control
• 1 MTM unit for internal-to-internal memory transfers
• Digital applications interface that includes four precision
• Digital peripheral interface that includes two timers, a 2-
prises an ALU, multiplier, shifter, and data register file
transfers between memory and the core at every core pro-
cessor cycle
The JTAG provides software debug through user break-
points which allows flexible exception handling.
buses for 32-bit data transfers
clock generators (PCG), a input data port (IDP/PDAP) for
serial and parallel interconnect, an S/PDIF receiver/trans-
mitter, four asynchronous sample rate converters, eight
serial ports, a flexible signal routing unit (DAI SRU).
wire interface, one UART, two serial peripheral interfaces
(SPI), 2 precision clock generators (PCG), pulse width
modulation (PWM), and a flexible signal routing unit (DPI
SRU).
on Page 1
shows the two clock domains that make
Figure 2
and detailed in the following
on Page 1
on Page
also shows the
5, the
Rev. PrA | Page 4 of 66 | March 2010
SIMD Computational Engine
The ADSP-2148x contains two computational processing ele-
ments that operate as a single-instruction, multiple-data
(SIMD) engine. The processing elements are referred to as PEX
and PEY and each contains an ALU, multiplier, shifter, and reg-
ister file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both pro-
cessing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive DSP algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the
bandwidth between memory and the processing elements.
When using the DAGs to transfer data in SIMD mode, two data
values are transferred with each access of memory or the regis-
ter file.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-
ments. These computation units support IEEE 32-bit single-
precision floating-point, 40-bit extended precision floating-
point, and 32-bit fixed-point data formats.
Timer
The processor contains a core timer that can generate periodic
software interrupts. The core timer can be configured to use
FLAG3 as a timer expired signal.
Data Register File
A general-purpose data register file is contained in each pro-
cessing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the processor’s enhanced Harvard
architecture, allow unconstrained data flow between computa-
tion units and internal memory. The registers in PEX are
referred to as R0-R15 and in PEY as S0-S15.
Context Switch
Many of the processor’s registers have secondary registers that
can be activated during interrupt servicing for a fast context
switch. The data registers in the register file, the DAG registers,
and the multiplier result registers all have secondary registers.
The primary registers are active at reset, while the secondary
registers are activated by control bits in a mode control register.
Preliminary Technical Data