uda1355h-n2 NXP Semiconductors, uda1355h-n2 Datasheet - Page 50

• Manufacturer Part Number: uda1355h-n2
• Description: Stereo Audio Codec With Spdif Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 49 Mixer gain setting
Note
1. See Table 52.
Table 50 De-emphasis setting for the incoming signal
Table 51 Register address 14H
Table 52 Description of register bits (address 14H)
2003 Apr 10
Symbol
Default
Symbol
Default
9 and 8 DAC_CH1_SEL[1:0]
11 and
Stereo audio codec with SPDIF interface
BIT
BIT
BIT
15
14
13
12
10
DE2_2
DE1_2
MIX
1
1
0
0
0
0
1
DA_POL_INV
SEL_NS
MIX_POS
MIX
DAC_CH2_SEL[1:0]
DA_POL_
SILENCE
(1)
INV
15
0
7
0
SYMBOL
SDET_ON
SEL_NS
MIX_GAIN
14
1
6
0
DE2_1
DE1_1
0
1
0
0
1
1
0
DAC polarity control. If this bit is logic 0 then the DAC output is not inverted; if this
bit is logic 1 then the DAC output is inverted.
Select noise shaper. If this bit is logic 0 then the third order noise shaper is
selected; if this bit is logic 1 then the fifth order noise shaper is selected.
Mixer position. Mixing is done before or after the sound processing unit (see
Table 53).
Mixer. If this bit is logic 0 then the mixer is disabled; if this bit is logic 1 then the mixer
is enabled (see Tables 48, 49 and 53).
DAC channel 2 input selection. Value to select the input mode to channel 2 of the
interpolator (see Table 54).
DAC channel 1 input selection. Value to select the input mode to channel 1 of the
interpolator (see Table 54).
MIX_POS
VALUE1
SD_
13
0
5
0
DAC output gain is set to 0 dB and mixer signal output gain is set 6 dB
DAC output gain and mixer signal output gain are set to 0 dB
DE2_0
DE1_0
VALUE0
0
1
0
1
0
SD_
MIX
12
0
4
0
50
DAC_CH2_
BASS_SEL
DESCRIPTION
SEL1
MIXER OUTPUT GAIN
11
1
3
0
DAC_CH2_
BYPASS
SEL0
10
1
2
0
FUNCTION
44.1 kHz
32 kHz
48 kHz
96 kHz
off
DAC_CH1_
Preliminary specification
OS_IN1
SEL1
9
0
1
0
UDA1355H
DAC_CH1_
OS_IN0
SEL0
8
1
0
0