uda1355h-n2 NXP Semiconductors, uda1355h-n2 Datasheet - Page 36

• Manufacturer Part Number: uda1355h-n2
• Description: Stereo Audio Codec With Spdif Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
11.3
Each byte (8 bits) is transferred with the MSB first (see
Table 20).
Table 20 Byte transfer
11.4
A device generating a message is a transmitter; a device
receiving a message is the receiver. The device that
controls the message is the master and the devices which
are controlled by the master are the slaves.
11.5
The register addresses in the I
as in the L3-bus mode.
11.6
Before any data is transmitted on the I
which should respond is addressed first. The addressing is
always done with the first byte transmitted after the start
procedure. The device address can be one of two, being
set by bit A0 which corresponds to pin MODE1.
The UDA1355H acts as a slave receiver or a slave
transmitter. Therefore, the clock signal SCL is only an
input signal. The data signal SDA is a bidirectional line.
The UDA1355H slave address is shown in Table 21.
Table 21 I
2003 Apr 10
handbook, full pagewidth
MSB
A6
Stereo audio codec with SPDIF interface
7
0
Byte transfer
Data transfer
Register address
Device address
A5
6
0
2
C-bus slave address
DEVICE ADDRESS
A4
5
1
SDA
SCL
A3
4
1
START condition
BIT
2
A2
C-bus mode are the same
3
0
S
Fig.18 START and STOP conditions on the I
2
A1
2
1
C-bus, the device
A0
A0
1
LSB
R/W
0/1
0
36
11.7
Both data and clock line will remain HIGH when the bus in
not busy. A HIGH-to-LOW transition of the data line, while
the clock is HIGH, is defined as a start condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as a stop condition (P); (see Fig.18).
11.8
The number of data bits transferred between the start and
stop conditions from the transmitter to receiver is not
limited. Each byte of eight bits is followed by one
acknowledge bit (see Fig.19). At the acknowledge bit the
data line is released by the master and the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter.
The device that acknowledges has to pull-down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse. Set-up and hold times
must be taken into account. A master receiver must signal
an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of
the slave. In this event the transmitter must leave the data
line HIGH to enable the master to generate a stop
condition.
Start and stop conditions
Acknowledgment
STOP condition
2
C-bus.
P
MBC622
Preliminary specification
SDA
SCL
UDA1355H