uda1355h-n2 NXP Semiconductors, uda1355h-n2 Datasheet - Page 25
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uda1355h-n2
Manufacturer Part Number
uda1355h-n2
Description
Stereo Audio Codec With Spdif Interface
Manufacturer
NXP Semiconductors
Datasheet
1.UDA1355H-N2.pdf
(76 pages)
- Current page: 25 of 76
- Download datasheet (316Kb)
Philips Semiconductors
2003 Apr 10
MODE
9
10
11
12
13
14
15
Stereo audio codec with SPDIF interface
Data path:
Features:
Data path:
Features:
Not used
See microcontroller mode
See microcontroller mode
See microcontroller mode
Not used
Input SPDIF to output I
Input I
Possibility to process input SPDIF, via
I
then to outputs DAC or SPDIF
BCK and WS being master for both I
input and output (different clocks)
Input I
BCK and WS being master; clocks
based on crystal oscillator
Microcontroller mode:
– DAC sound features can be used
– SPDIF output channel status bits
Input SPDIF to output DAC or I
Input I
Possibility to process input SPDIF, via
I
then to output SPDIF
Input SPDIF to outputs I
locking onto the SPDIF input signal;
BCK and WS being master
Input I
WS being master; clocks are
generated by the crystal oscillator
Microcontroller mode:
– DAC sound features can be used
– SPDIF input channel status bits
– SPDIF output channel status bits
2
2
S-bus using an external DSP and
S-bus using an external DSP and
(two times 40) setting.
(two times 40) can be read
(two times 40) setting.
2
2
2
2
S to outputs DAC or SPDIF.
S to outputs DAC and SPDIF;
S-bus to output SPDIF.
S to output SPDIF; BCK and
FEATURES
2
S
2
S and DAC;
2
S
2
S
25
XTAL
XTAL
I
SPDIF IN
2
I
SPDIF IN
S INPUT
2
S INPUT
(e.g. Sample Rate Convertor)
(e.g. Sample Rate Convertor)
I
2
I
S slave
2
EXTERNAL DSP
S slave
EXTERNAL DSP
SCHEMATIC
(SAA7715)
(SAA7715)
PLL
PLL
I
SPDIF OUT
2
I
SPDIF OUT
2
S OUTPUT
MGU845
S OUTPUT
SPDIF LOCK
MGU846
Preliminary specification
SPDIF LOCK
DAC
I
DAC
2
I
2
S master
UDA1355H
S master
MUTE
MUTE
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