uda1355h-n2 NXP Semiconductors, uda1355h-n2 Datasheet - Page 4

• Manufacturer Part Number: uda1355h-n2
• Description: Stereo Audio Codec With Spdif Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
2
The UDA1355H is a single-chip IEC 60958 decoder and
encoder with integrated stereo digital-to-analog converters
and analog-to-digital converters employing bitstream
conversion techniques.
The UDA1355H has a selectable one-of-four SPDIF input
(accepting level I, II and III timing) and one SPDIF output
3
2003 Apr 10
UDA1355H
Programmable digital silence detector
Interpolating filter (f
recursive and a FIR filter in cascade
Selectable fifth-order noise shaper operating at 64f
third-order noise shaper operating at 128f
low sampling frequencies, e.g. 16 kHz) generating
bitstream for DAC
Filter Stream DAC (FSDAC)
In microcontroller mode:
– Left and right volume control (for balance control)
– Left and right bass boost and treble control
– Optional resonant bass boost control
– Mixing possibility of two data streams.
Stereo audio codec with SPDIF interface
NUMBER
GENERAL DESCRIPTION
ORDERING INFORMATION
0 to 78 dB and
TYPE
s
QFP44
NAME
to 64f
s
or f
s
plastic quad flat package; 44 leads (lead length 1.3 mm); body
10
to 128f
10
s
) comprising a
s
(specially for
1.75 mm
s
or
4
DESCRIPTION
which can generate level II output signals with CMOS
levels. In microcontroller mode the UDA1355H offers a
large variety of possibilities for defining signal flows
through the IC, offering a flexible analog, digital and SPDIF
converter chip with possibilities for off-chip sound
processing via the digital input and output interface.
A lock indicator is available on pin LOCK when the
IEC 60958 decoder and the clock regeneration
mechanism is in lock. By default the DAC output and the
digital data interface output are muted when the decoder
is not in lock.
The UDA1355H contains two clock systems which can run
at independent frequencies, allowing to lock-on to an
incoming SPDIF or digital audio signal, and in the mean
time generating a stable signal by means of the crystal
oscillator for driving, for example, the ADC or SPDIF
output signal.
Using the crystal oscillator (which requires a 12.288 MHz
crystal) and the on-chip low jitter PLL, all standard audio
sampling frequencies (f
half and double these frequencies) can be generated.
PACKAGE
s
= 32, 44.1 and 48 kHz including
Preliminary specification
UDA1355H
SOT307-2
VERSION