uda1355h-n2 NXP Semiconductors, uda1355h-n2 Datasheet - Page 3

• Manufacturer Part Number: uda1355h-n2
• Description: Stereo Audio Codec With Spdif Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
1
1.1
1.2
1.3
1.4
2003 Apr 10
2.7 to 3.6 V power supply
Integrated digital interpolator filter and Digital-to-Analog
Converter (DAC)
24-bit data path in interpolator
No analog post filtering required for DAC
Integrated Analog-to-Digital Converter (ADC),
Programmable Gain Amplifier (PGA) and digital
decimator filter
24-bit data path in decimator
Master or slave mode for digital audio data I/O interface
I
and 24 bits formats supported on digital I/O interface.
Controlled by means of static pins or microcontroller
(L3-bus or I
On-chip amplifier for converting IEC 60958 input to
CMOS levels
Supports level I, II and III timing
Selectable IEC 60958 input channel, one of four
Supports input frequencies from 28 to 96 kHz
Lock indication signal available on pin LOCK
40 status bits can be read for left and right channel via
L3-bus or I
Channel status bits available via L3-bus or I
pre-emphasis, audio sample frequency, two channel
Pulse Code Modulation (PCM) indication and clock
accuracy
Pre-emphasis information of incoming IEC 60958
bitstream available in register
Detection of digital data preamble, such as AC3,
available on pin in microcontroller mode.
CMOS output level converted to IEC 60958 output
signal
Full-swing digital signal, with level II timing using crystal
oscillator clock
32, 44.1 and 48 kHz output frequencies supported in
static mode
Stereo audio codec with SPDIF interface
2
S-bus, MSB-justified, LSB-justified 16, 18, 20,
FEATURES
General
Control
IEC 60958 input
IEC 60958 output
2
2
C-bus
C-bus) interface.
2
C-bus: lock,
3
1.5
1.6
1.7
32, 44.1 and 48 kHz output frequencies (including
double and half of these frequencies) supported in
microcontroller mode
Via microcontroller, 40 status bits can be set for left and
right channel.
Supports sampling frequencies from 16 to 100 kHz
Supported static mode:
– I
– LSB-justified 16 and 24 bits format
– MSB-justified format.
Supported microcontroller mode:
– I
– LSB-justified 16, 18, 20 or 24 bits format
– MSB-justified format.
BCK and WS signals can be slave or master, depending
on application mode.
Supports sampling frequencies from 16 to 100 kHz
Analog front-end includes a 0 to +24 dB PGA in steps of
3 dB, selectable via microcontroller interface
Digital independent left and right volume control of
+24 to 63.5 dB in steps of 0.5 dB via microcontroller
interface
Bitstream ADC operating at 64f
Comb filter decreases sample rate from 64f
Decimator filter (8f
FIR half-band filters.
Digital de-emphasis for 32, 44.1, 48 and 96 kHz audio
sampling frequencies
Automatic de-emphasis when using IEC 60958 to DAC
Soft mute made of a cosine roll-off circuit selectable via
pin MUTE or L3-bus interface
2
2
S-bus format
S-bus format
Digital I/O interface
ADC digital sound processing
DAC digital sound processing
s
to f
s
) made of a cascade of three
Preliminary specification
s
UDA1355H
s
to 8f
s