uda1355h-n2 NXP Semiconductors, uda1355h-n2 Datasheet - Page 30
uda1355h-n2
Manufacturer Part Number
uda1355h-n2
Description
Stereo Audio Codec With Spdif Interface
Manufacturer
NXP Semiconductors
Datasheet
1.UDA1355H-N2.pdf
(76 pages)
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Philips Semiconductors
2003 Apr 10
MODE
Stereo audio codec with SPDIF interface
12
13
14
15
Data path:
Features:
Data path:
Features
Data path:
Features:
Not used
Input ADC to outputs I
Inputs I
BCK and WS of I
Inputs SPDIF and I
with mixing/selection possibility; clocks
are generated from SPDIF input signal,
and BCK and WS are master
SPDIF input channel status bits (two
times 40) can be read
SPDIF output channel status bits (two
times 40) setting.
Input ADC to output I
Inputs I
or SPDIF.
BCK and WS being master
SPDIF input channel status bits (two
times 40) can be read
Output SPDIF supported but the timing
not according to level II
Output SPDIFOUT loop through can
be selected with independent SPDIF
input channel select.
Inputs ADC and I
SPDIF and I
All clocks are related to WS signal of
I
Master BCK and WS for I
slave BCK and WS for I
SPDIF output channel status bits (two
times 40) can be set; level II timing
depends on the I
2
S-bus input
2
2
S and SPDIF to output DAC.
S and SPDIF to outputs DAC
2
FEATURE
S.
2
2
2
S-bus clocks.
S output are master
S to outputs DAC
2
S to output DAC
2
S
2
S or SPDIF
2
S input
2
S output;
I
I
I
2
2
2
S slave
S slave
S slave
30
I
ADC
2
ADC
ADC
S INPUT
I
XTAL
XTAL
2
SPDIF IN
I
S INPUT
SPDIF IN
2
S INPUT
SCHEMATIC
PLL
PLL
PLL
I
SPDIF
2
I
I
SPDIF OUT
SPDIF OUT
2
OUT
2
Preliminary specification
S OUTPUT
S OUTPUT
S OUTPUT
SPDIF LOCK
SPDIF LOCK
I
2
S LOCK
UDA1355H
DAC
DAC
DAC
MGU852
MGU851
MGU853
MUTE
SPDIF OUT
I
MUTE
I
MUTE
I
2
2
2
S master
S master
S master
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