idt49c465apqfb Integrated Device Technology, idt49c465apqfb Datasheet - Page 9

• Manufacturer Part Number: idt49c465apqfb
• Description: 32-bit Flow-thru Error Detection Correction Unit
• Manufacturer: Integrated Device Technology

IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
DIAGNOSTIC DATA FORMAT (SYSTEM BUS)
DIAGNOSTIC FEATURES — DETAILED DESCRIPTION
31
S
Error
Type
Mode 2-0
30
M
x11
x10
000
x01
100
served
-
Re-
-
Byte 3
“NORMAL” Mode
In this mode, operation is “Normal” or non-diagnostic.
“GENERATE-DETECT” Mode
When the EDC unit is in the “Generate-Detect” Mode, data is not corrected or altered by the error correction network.
(Also referred to as the “Detect-only” Mode.)
“ERROR-DATA-OUTPUT” Mode
In this mode, the 32-bit data from the Error-Data Register is output on the SD bus.
Error Data Register: The uncorrected data from the Memory Data bus input latch is stored in the Error-Data Register
if the error counter contents indicates “0” and there is a positive transition on the SYNCLK input when the
low. Thus, the Error-Data Register contains memory data corresponding to the first error to occur since the register was
cleared. This register is cleared by pulling the
the “Error-Data-Output” Mode and enabling the System Data bus output drivers.
All-Zero-Data: The Error-Data Register can be used as an “all-zero-data” data source for memory initialization in systems
where the initialization process is to be done entirely by hardware.
“DIAGNOSTIC-OUTPUT” Mode
In this mode, data from the diagnostic registers, the PCBI bus and the CBI bus is output on the SD bus.
Direct Checkbit Readback: Internal data paths allow both the “Partial-CheckBit-Input” bus and the data in the “CheckBit-
Input” latch to be read directly by the system bus for diagnostic purposes. Both the Checkbit Input Bus and the Partial
Checkbit Input Bus are read via the System Data bus by entering the “Diagnostic-Output” Mode and enabling the System
Data bus output drivers. The checkbits are output on System Data bus bits 0-7; the Partial Checkbits are output on bits
8-15.
Syndrome Register: After an error has been detected, the syndrome bits generated are clocked into the internal
Syndrome Register if the error counter contents indicates “0” and there is a positive transition on the SYNCLK input when
the
bus by entering the “Diagnostic-Output” Mode and enabling the System Data bus outputs. This data is output on SD
bits 16-23.
Error Counter: The 4-bit on-board error counter is incremented if the error counter contents do not indicate FF HEX, which
corresponds to a count of 15, and there is a positive transition on the SYNCLK input when the
counter is cleared by pulling the
“Diagnostic-Output” Mode and enabling the System Data bus output drivers. This data is output on System Data bus
bits 24-27.
Test Register: These 2 bits are reserved for factory diagnostics only and must not be used by system software. This data
is output on System Data bus bits 28-29.
Error-Type Register: The Error-Type Register, clocked by the SYNCLK input, saves 2 bits which indicate whether a
recorded error was a single or a multiple-bit error. This register holds only the first error type to occur after the last Clear
operation. This data is output on System Data bus bits 30-31.
Direct Read-Path Checkbit Injection: In the “Checkbit-Injection” Mode, bits 0-7 of the System Data input latch are
presented to the inputs of the Checkbit Input latch. If MLE is strobed, the checkbit latch will be loaded with this value in
place of the checkbits from memory. By inserting various checkbit values, operation of the correction function of the EDC
can be verified “on-board”. Except for the “Checkbit-Injection” function, operation in this mode is identical to “Normal” Mode
operation.
27
2
3
ERR
Counter
2
Error
2
signal is low. This register is cleared by pulling the
2
Latched Data
1
2
24 23
0
7
6
Syndrome bits
5
4
Byte 2
CLEAR
3
2
input low. The counter is read via the System Data bus by entering the
1
CLEAR
16 15
0
11.7
7
input low. The register is read via the System Data bus by entering
6
CLEAR
Partial Checkbits
5
MILITARY AND COMMERCIAL TEMPERATURE RANGES
4
Byte 1
input low. The register is read via the System Data
3
Data Out (Unlatched)
2
1
0
8 7
7
6
ERR
5
Checkbits
Byte 0
signal is low. This
4
3
ERR
2
signal is
2552 drw 12
2552 tbl 03
1
9
0
0