idt49c465apqfb Integrated Device Technology, idt49c465apqfb Datasheet - Page 7

• Manufacturer Part Number: idt49c465apqfb
• Description: 32-bit Flow-thru Error Detection Correction Unit
• Manufacturer: Integrated Device Technology

IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
PIN DESCRIPTIONS
I/O Buses and Controls
SD
SD
SD
SD
SLE
PLE
SOE
BE
MD
MLE
MOE
P
PSEL
Inputs
CBI
PCBI
CODE ID
0-3
Symbol
0-3
0-7
8-15
16-23
24-31
0-31
0-7
0-7
1,0
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
System Data Bus: Data from MD
rected in the other modes. The BE
output buffers during a read cycle. (Also, see diagnostic section.)
Separate I/O memory systems: In a write or partial-write cycle, the byte not-to-be-modified is output on
SD
are input on the SD
Bi-directional memory systems: In a write or partial-write cycle, the byte not-to-be-modified is re-directed
to the MD I/O pins, if BE
must be high to avoid enabling the output drivers to the system bus in this mode. The new bytes to be written
are input on the SD
data from the System Data bus to the MD I/O pins for checkbit generation and writing to the checkbit memory.
System Latch Enable: SLE is an input used to latch data at the SD inputs. The latch is transparent when
SLE is high; the data is latched when SLE is low.
Pipeline Latch Enable:
the SD bus and the MD bus during byte merges. Use of this latch is optional. The latch is transparent when
PLE
System Output Enable: When low, enables System output drivers and Parity output drivers if correspond-
ing Byte Enable inputs are high.
Byte Enables: In systems using separate I/O memory buses, BE
outputs for byte n. The BE
data from the Memory Data latch is directed to the MD I/O pins and used for checkbit generation for byte
n. This is used in partial-word-write operations or during correction cycles. When BE
the System Data latch is directed to the MD I/O pins and used for checkbit generation for byte n.
Memory Data Bus: These I/O pins accept a 32-bit data word from main memory for error detection and/
or correction. They also output corrected old data or new data to be written to main memory when the EDC
unit is used in a bi-directional configuration.
Memory Latch Enable: MLE is used to latch data from the MD inputs and checkbits from the CBI inputs.
The latch is transparent when MLE is high; data is latched when MLE is low. When identified as the upper
slice in a 64-bit cascade, the checkbit latch is bypassed.
Memory Output Enable:
Parity I/O: The parity I/O pins for Bytes 0 to 3. These pins output the parity of their respective bytes when
that byte is being output on the SD bus. These pins also serve as parity inputs and are used in generating
the Parity ERRor (
even depending on the state of the Parity SELect pin (PSEL).
Parity SELect:
CheckBits-In (00)
In a single EDC system or in the lower slice of a cascaded EDC system, these inputs accept the checkbits
from the checkbit memory. In the upper slice in a cascaded EDC system, these inputs accept the “Partial-
Syndrome” from the lower slice (Detect/Correct path).
Partial-CheckBits-In (10)
In a single EDC system, these inputs are unused but should not be allowed to float. In a cascaded EDC
system, the “Partial-Checkbits” used by the lower slice are accepted by these inputs (Correction path only).
In the upper slice of a cascaded EDC system, “Partial-Checkbits” generated by the lower slice are accepted
by these inputs (Generate path).
CODE IDentity: Inputs which identify the slice position/ functional mode of the IDT49C465.
(00) Single 32-bit EDC unit
(01) 64-bit “Checkbit-generate-only” unit
n
to n+7 for re-writing to memory, if BE
is low; the data is latched when
BE
BE
PERR
If the Parity SELect pin is low, the parity is even.
If the Parity SELect pin is high, the parity is odd.
n
n
pins for checkbit generation and writing to memory. BE
pins, for writing checkbits to memory, if BE
0
1
controls SD
controls SD
n
) signal under certain conditions (see Byte Enable definition). The parity is odd or
is high, for checkbit generation and rewriting to memory via the MD I/O pins.
PLE
n
MOE
pins also control the “Byte mux”. When BE
is an input which controls a pipeline latch, which controls data to be output on
enables Memory Data Bus output drivers when low.
0-7
8-15
CheckBits-In-1 (10)
Partial-CheckBits-In (11):
0-31
n
11.7
inputs must be high and the
PLE
Name and Function
appears at these pins corrected if MODE 2-0 = x11, or uncor-
n
is high.
is high and
BE
BE
(10) Lower slice of a 64-bit cascade
(11) Upper slice of a 64-bit cascade
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SOE
2
3
controls SD
controls SD
is low. The new bytes to be written to memory
n
SOE
is low.
n
24-31
16-23
n
is used to enable the SD and Parity
is high, the corrected or uncorrected
Partial-Syndrome-In (11):
pin must be low to enable the SD
n
must be low to direct input
n
is low, the data from
2552 tbl 01
SOE
7