idt49c465apqfb Integrated Device Technology, idt49c465apqfb Datasheet - Page 30

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idt49c465apqfb

Manufacturer Part Number
idt49c465apqfb
Description
32-bit Flow-thru Error Detection Correction Unit
Manufacturer
Integrated Device Technology
Datasheet
IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
AC TIMING DIAGRAMS — 32-BIT CONFIGURATION
NOTE:
1. Assumes that Memory Data and Checkbits are valid at least 3ns (Com.)/4ns (Mil.) before MLE goes HIGH.
MD
MOE
SOE
MLE
PLE
P
0–31
BE
CBI
0–3
N
(OUTPUT)
to
to
t BESZx
t SESZx
t MEMxZ
1
1
t BEPZx
t SEP
Valid Checkbits In
Valid DATA
t MMLS
t CMLS
t MLS
t PLS
t MLP
t PLP
t MP
(1)
(1)
t CS
t MS
2
2
t MMLH
t CMLH
IN
Parity Out
3
3
Corrected DATA
Figure 9. 32-Bit Correct Timing
4
4
11.7
OUT
5
5
Parameter
t MEMxZ
t MMLS
t MMLH
t CMLS
t CMLH
t MLS
t PLS
t BESZx
t SESZx
t CS
t MS
t MP
t MLP
t PLP
t BEPZx
t SEP
Name
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(1)
(1)
MOE = High to MD
MD
MD
Checkbit Set-up to MLE = Low
Checkbit Hold to MLE = Low
MLE
PLE = Low to SD
BE
SOE = Low to SD
CBI to Corrected SD
MD
MD
MLE = High to Parity Out
PLE = Low to Parity Out
BE
SOE = Low to Parity Out
From
N
N
IN
IN
IN
IN
IN
= High to SD
= High to Parity Out
Set-up to MLE = Low
Hold to MLE = Low
to Corrected SD
to Parity Out
Propagation Delay
= High to SD
OUT
OUT
OUT
OUT
OUT
OUT
(1)
Enabled
Enabled
OUT
Disabled
(1)
To
2552 drw 21
Min./
Max.
max.
min.
min.
min.
min.
max.
max.
max.
max.
max.
max.
max.
max.
max.
max.
max.
30

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