idt49c465apqfb Integrated Device Technology, idt49c465apqfb Datasheet - Page 5

• Manufacturer Part Number: idt49c465apqfb
• Description: 32-bit Flow-thru Error Detection Correction Unit
• Manufacturer: Integrated Device Technology

IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
SYSTEM CONFIGURATIONS
configurations in an EDC system. The basic configurations
are shown below.
most appropriate for systems using bidirectional memory
buses. It is the simplest configuration to understand and use.
During a correction cycle, the corrected data word can be
simultaneously output on both the system bus and memory
bus. Logically, no other parts are required for the correction
function. During partial-word-write operations, the new bytes
are internally combined with the corrected old bytes for
checkbit generation and writing to memory.
appropriate for systems using separate I/O memory buses.
This configuration allows separate input and output memory
buses to be used. Corrected data is output on the SD outputs
for the system and for re-write to memory. Partial word-write
bytes are combined externally for writing and checkbit
generation.
CPU
The IDT49C465 EDC unit can be used in various
Figure 1 illustrates a bidirectional configuration, which is
I/O
Figure 2 illustrates a separate I/O configuration. This is
CPU
Figure 1. Common I/O Configuration
Figure 2. Separate I/O Configuration
SD
EDC
EDC
CBO
CBI
MD
SD
CBO
CBI
MD
MEMORY
CHECKBITS
CHECKBITS
OUTPUTS
MEMORY
MEMORY
I/O
INPUTS
2552 drw 06
2552 drw 05
11.7
external buffers and is also well suited for systems using
memory with separate I/O buses. Since data from memory
does not need to pass through the part on every cycle, the
EDC system may operate in “bus-watch” mode. As in the
separate I/O configuration, corrected data is output on the SD
outputs.
very fast 64-bit checkbit generation in systems that use
separate checkbit-generate and detect-correct units. If this is
not desired, 64-bit checkbit generation and correction can be
done with just 2 EDC units. 64-bit correction is also straight-
forward, fast and requires no extra hardware for the
expansion.
EXT.BUFFER
Figure 3 illustrates a third configuration which utilizes
Figure 4 illustrates the single-chip generate-only mode for
INPUT BUS
EXT. BUFFER
MEMORY
BUFFER
INPUT BUS
MEMORY
Figure 3. Bypassed Separate I/O Configuration
Figure 4. Separate Generate/Correction Units
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BITS OUT
CHECK
with 64-Bit Checkbit Generation
64-BIT
ONLY
GEN.
EDC
CBO
SD
CBO
CHECKBIT
INPUT BUS
MEMORY
CPU BUS
CPU BUS
BUFFER
EDC
I/O
CHECK
BITS IN
CBI
MD
BUFFER
CBI
EXT. BUFFER
LOWER
DATA
EDC
OUTPUT BUS
MEMORY
OUTPUT BUS
MEMORY
2552 drw 07
UPPER
BUFFER
2552 drw 08
DATA
EDC
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