IDT49C465 Integrated Device Technology, Inc., IDT49C465 Datasheet
IDT49C465
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IDT49C465 Summary of contents
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... FLOW-THRU ERROR DETECTION AND CORRECTION UNIT DESCRIPTION The IDT49C465 32-bit, two-data bus, Flow-thruEDC unit. The chip provides single-error correction and two and three bit error detection of both hard and soft memory errors. It can be expanded to 64-bit widths by cascading two units, without the need for additional external logic ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT PIN CONFIGURATION GND SLE PLE SOE GND GND ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT PIN CONFIGURATION V SD PCBI PCBI PCBI GND SLE SOE PLE GND ...
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ERROR ERR DETECT MERR 8 SYO MUX 0–7 PLE SOE 4 BE 0– BYTES SD 0–31 SD LATCH SLE PSEL PARITY 4 GEN 4 P 0–3 PARITY 4 CHECK PERR /ERR INTERNAL SYNCLK SYNCLK SCLKEN CLEAR 2 ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT SYSTEM CONFIGURATIONS The IDT49C465 EDC unit can be used in various configurations in an EDC system. The basic configurations are shown below. Figure 1 illustrates a bidirectional configuration, which is most appropriate for systems using bidirectional memory buses the simplest configuration to understand and use. ...
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... PARTIAL–CHECKBITS–OUT (10) PARTIAL–CHECKBITS–OUT (10) (GENERATE ONLY) (GENERATE ONLY) 8 PARTIAL–SYNDROME (DETECT/CORRECT ONLY) Figure 6. 64-Bit Mode — 2 Cascaded IDT49C465 Devices device on the SD full 64-bit word from memory. checkbits are output on the CBO 0-31 time is less than that resulting from using a two-chip cascade. MD 0– ...
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... In the upper slice of a cascaded EDC system, “Partial-Checkbits” generated by the lower slice are accepted by these inputs (Generate path). CODE ID I CODE IDentity: Inputs which identify the slice position/ functional mode of the IDT49C465. 1,0 (00) Single 32-bit EDC unit (01) 64-bit “Checkbit-generate-only” unit ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT PIN DESCRIPTIONS (Con’t.) Symbol I/O Inputs (Con’t.) MODE I MODE select: Selects one of five operating modes. 2-0 (x11) “Normal” Mode: Normal EDC operation (Flow-thru correction and generation). (x10) “Generate-Detect” Mode: In this mode, error correction is disabled. Error generation and detection are normal ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT DIAGNOSTIC DATA FORMAT (SYSTEM BUS) Latched Data Error Re- Error Type served Counter Byte DIAGNOSTIC FEATURES — DETAILED DESCRIPTION Mode 2-0 x11 “NORMAL” Mode In this mode, operation is “Normal” or non-diagnostic. ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT OPERATING MODE CHARTS SLICE IDENTIFICATION CODE ID 1 CODE ID 0 Slice Definition 0 0 32-bit Flow-Thru EDC 0 1 64-bit GENERATE Only EDC 1 0 64-bit EDC- Lower 32 bits (0-31 64-bit EDC- Upper 32 bits (32-63) SLICE POSITION CONTROL ...
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... CPU SD MAIN MEMORY P D OUT IDT49C465 CHECKBIT MEMORY 2. Data Correction Read Memory Word D IN CORRECTED SD CPU MAIN MEMORY P D OUT IDT49C465 CHECKBIT MEMORY 3. Memory Generation Re-write Corrected Word to Memory D IN CORRECTED SD CPU MAIN MEMORY P D OUT IDT49C465 CHECKBIT MEMORY 11.7 MD I/O MAIN MEMORY ...
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... GENERATOR IDT49C465 The example shown above illustrates the case of combin- ing three bytes from an old word with a new lower order byte to form a new word. The new word, along with the new checkbits, may now be written to memory. In the separate I/O memory configuration, the situation is similar except that the new word is output on the SD Bus instead of the MD Bus (refer to previous page) ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT 32-BIT DATA WORD CONFIGURATION A single IDT49C465 EDC unit, connected as shown below, provides all the logic needed for single-bit error correction, and double-bit error detection 32-bit data field. The identification code (00) indicates seven checkbits are re- quired ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT 64-BIT DATA WORD CONFIGURATION Two IDT49C465 EDC units, connected as shown below, provide all the logic needed for single-bit error correction, and double-bit error detection 64-bit data field. The “Slice Identification” Table gives the CODE ID1,0 values needed for distinguishing the upper 32 bits from the lower 32 bits ...
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... Final Internal Syndrome bits 0 7 FUNCTIONAL EQUATIONS: The equations below describe the terms used in the IDT49C465 to determine the values of the partial checkbits, checkbits, partial syndromes and final internal syndromes. NOTE: All “ ” symbols below represent the “EXCLUSIVE- OR” function ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT DETAILED DESCRIPTION — CHECKBIT AND SYNDROME GENERATION vs. CODE ID LOGIC EQUATIONS FOR THE CBO OUTPUTS CODE ID 1,0 Checkbit 00 10 Generation Final Chkbits Partial Checkbits CBO CBO CBO CBO 3 CBO PD PD ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT DETAILED DESCRIPTION — 32-BIT CONFIGURATION 32-BIT MODIFIED HAMMING CODE — CHECKBIT ENCODING CHART Generated Checkbits Parity CB0 Even (XOR) CB1 Even (XOR) CB2 Odd (XNOR) CB3 Odd (XNOR) CB4 Even (XOR) CB5 Even (XOR) ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT DETAILED DESCRIPTION — 64-BIT CONFIGURATION 64-BIT MODIFIED HAMMING CODE - CHECKBIT ENCODING CHART Generated Checkbits Parity CB0 Even (XOR) CB1 Even (XOR) CB2 Odd (XNOR) CB3 Odd (XNOR) CB4 Even (XOR) CB5 Even (XOR) ...
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... Total AC Delay for IDT49C465 in 64-bit Mode (L) = Lower slice (U) = Upper slice SD to CBO(L) + PCBI to CBO(U) t SC( PCC( SYO(L) + CBI to t MSY( ( SYO(L) + CBI to t MSY( CME ( MD to SYO(L) + CBI to SD(U) t MSY( (U) (or) ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT ABSOLUTE MAXIMUM RATINGS Symbol Rating Com’l. V Power Supply –0.5 to +7.0 –0.5 to +7.0 CC Voltage V Terminal Voltage –0.5 to TERM with Respect Ground T Operating 0 to +70 A Temperature T Temperature –55 to +125 –65 to +135 BIAS Under Bias ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Con’t.) The following conditions apply unless otherwise specified: Commercial + Symbol Parameter I Quiescent Power Supply Current CCQ CMOS Input Levels I Quiescent Power Supply Current ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT AC PARAMETERS - 49C465A PROPAGATION DELAY TIMES Parameter Description Number Parameter From To Name Input (edge) Output (edge) Max. GENERATE (WRITE) PARAMETERS PCC PPE XIN ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT AC PARAMETERS - 49C465A PROPAGATION DELAY TIMES FROM LATCH ENABLES Parameter Description Parameter From Number Name Input (edge MLC 23 t MLE 24 t MLE = MLME 25 t MLP 26 t MLS 27 t MLSY PLE PLS PLE ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT SET-UP AND HOLD TIMES - 49C465A Parameter Description Parameter From Number Name Input (edge SDIN Set-up * SSLS 43 t SDIN Hold SSLH 44 t MDIN Set-up * MMLS 45 t MDIN Hold MMLH 46 t CBI Set-up CMLS ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT Note 1: 64-bit Upper Slice Application Exception (49C465A) Parameter Description Parameter From Number Name Input 39(a) tMEMxZ MOE 44(a) tMMLS MDin Set-up 45(a) tMMLH MDIN Hold 46(a) tCMLS CBI Set-up 47(a) tCMLH CBI Hold Parameter Number Name Input + Conditions ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT AC PARAMETERS - 49C465 PROPAGATION DELAY TIMES Parameter Description Number Parameter From To Name Input (edge) Output (edge) Max. Max. Max. Max. Max. Max. Max. Max. Unit GENERATE (WRITE) PARAMETERS ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT AC PARAMETERS - 49C465 PROPAGATION DELAY TIMES FROM LATCH ENABLES Parameter Description Parameter From Number Name Input (edge MLC 23 t MLE 24 t MLE = HIGH MLME 25 t MLP 26 t MLS 27 t MLSY PLE LOW ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT SET-UP AND HOLD TIMES - 49C465 Parameter Description Parameter From Number Name Input 42 t SDIN Set-up SSLS 43 t SDIN Hold SSLH 44 t MDIN Set-up MMLS 45 t MDIN Hold MMLH 46 t CBI Set-up CMLS 47 t CBI Hold ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT Note 5: 64-bit Upper Slice Application Exception (49C465A) Parameter Description Parameter From Number Name Input 39(a) tMEMxZ MOE 44(a) tMMLS MDin Set-up 45(a) tMMLH MDIN Hold 46(a) tCMLS CBI Set-up 47(a) tCMLH CBI Hold Parameter Number Name Input + Conditions ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT AC TIMING DIAGRAMS — 32-BIT CONFIGURATION BESxZ t BESxZ SOE t SESxZ t SESxZ (OUTPUT) DATA SD 0–31 t SSLS SLE P N PERR t SM (1) t SLM MOE tMEMZx MD (INPUT) 0–31 t SLC CBOE t CECZx CBO to 1 NOTE: 1 ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT AC TIMING DIAGRAMS — 32-BIT CONFIGURATION to 1 MOE t MEMxZ (OUTPUT) Valid DATA MD 0–31 t MMLS CBI Valid Checkbits In t CMLS MLE t MLSY SYO t MLEx ERR MERR to 1 NOTE: 1. Assumes that Memory Data and Checkbits are valid at least 3ns (Com.)/4ns (Mil,) before MLE goes HIGH. ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT AC TIMING DIAGRAMS — 32-BIT CONFIGURATION to 1 MOE t MEMxZ Valid DATA (OUTPUT) MD 0–31 t MMLS CBI Valid Checkbits In t CMLS MLE t MLS PLE t PLS BESZx SOE t SESZx t MLP t PLP t BEPZx t SEP P 0–3 ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT AC TIMING DIAGRAMS — 64-BIT CONFIGURATION BOTH to 1 465s BE N SOE t SESxZ t SESxZ DATA (OUTPUT & SSLS SLE P x PERR t SM MOE (1) t SLM t MEMZx t BEM (INPUT & SLC CBOE ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT AC TIMING DIAGRAMS — 64-BIT CONFIGURATION to 1 BOTH 465s MOE t MEMxZ Valid DATA (OUTPUT) MD (L) t MMLS Valid Checkbits In CBI t CMLS MLE t MLS BESZx SOE t SESZx LOWER 465 SD 0–31 t MSY t CSY t MLSY SYO ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT AC TIMING DIAGRAMS — 64-BIT CONFIGURATION 64-BIT to 1 U/L Slice MOE t MEMxZ (OUTPUT) MD Valid DATA 0–31 t MMLS CBI Valid Checkbits In t CMLS MLE t MLS PCBI PLE t PLS BESZx SOE t SESZx SD 0–31 t MSY t MLP ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT AC TIMING DIAGRAMS — 64-BIT CONFIGURATION 64-BIT to 1 U/L Slice MOE t MEMxZ (OUTPUT) MD Valid DATA 0–31 t MMLS CBI Valid Checkbits In t CMLS MLE t MLS PLE t PLS BESZx SOE t SESZx SD 0–31 t MLP t PLP t BEPZx ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT AC TIMING DIAGRAMS — 64-BIT CONFIGURATION SINGLE to 1 465 SOE (SOE = Tied high) Valid DATA SD Bus t SSLS SLE t SLC (MOE = Tied high) MOE Valid DATA MD Bus t MMLS MLE t MLC CBOE t CECZx CBO to 1 NOTE: 1 ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT AC TIMING DIAGRAMS — DIAGNOSTIC TIMING to 1 465 Checkbits In CBI t CSCS Memory DataIN MD Bus t MSCS MLE t MLSCS SCLKEN t SESCS SYNCLK t CLEAR CLEAR SD Bus to 1 Parameter CSCS t MSCS t MLSCS t SESCS t SESCH t SESCH t SYNCLK ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS OUT IN Pulse D.U.T. Generator R T SET-UP, HOLD AND RELEASE TIMES DATA INPUT t SU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET ...
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... IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT ORDERING INFORMATION IDT XX 49C465 Package Device Type Speed XX X Process/ Temperature Range 11.7 MILITARY AND COMMERCIAL TEMPERATURE RANGES BLANK Commercial ( + Military (– +125 C) PQF Plastic Quad Flatpack G Pin Grid Array ...