idt49c465apqfb Integrated Device Technology, idt49c465apqfb Datasheet - Page 8

• Manufacturer Part Number: idt49c465apqfb
• Description: 32-bit Flow-thru Error Detection Correction Unit
• Manufacturer: Integrated Device Technology

IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
PIN DESCRIPTIONS (Con’t.)
Inputs (Con’t.)
MODE
CLEAR
SYNCLK
SCLKEN
Outputs and Enables
CBO
CBOE
SYO
ERR
MERR
PERR
Power Supply Pins
Vcc
GND
Symbol
0-7
0-7
1- 10
1-12
2-0
I/O
O
O
O
O
O
P
P
I
I
I
I
I
(x11)
(x10)
(000)
(x01)
(100)
MODE select: Selects one of four operating modes.
“Normal” Mode: Normal EDC operation (Flow-thru correction and generation).
“Generate-Detect” Mode: In this mode, error correction is disabled. Error generation and detection are
normal.
“Error-Data-Output” Mode: Allows the uncorrected data captured from an error event by the Error-Data
Register to be read by the system for diagnostic purposes. The Error-Data Register is cleared by toggling
CLEAR
from the first error that occurs after they are reset by the
Register are updated when there is a positive edge on SYNCLK, an error condition is indicated (
and the Error Counter indicates zero.
All-Zero-Data Source: In Error-Data-Output Mode, clearing the Error-Data Register provides a source of
all-zero-data for hardware initialization of memory, if this desired.
Diagnostic-Output Mode: In this mode, the contents of the Syndrome Register , Error Counter and Error-
Type Register are output on the SD bus. This allows the syndrome bytes for an indicated error to be read
by the system for error-logging purposes. The Syndrome Register and the Error-Data Register are updated
when there is a positive edge on SYNCLK, an error condition is indicated and the Error Counter indicates
zero errors. Thus, the Syndrome Register saves the syndrome that was present when the first error occurred
after the Error Counter was cleared. The Syndrome Register and the Error Counter are cleared by toggling
CLEAR
the Syndrome Register or Error-Data Register was read.
Checkbit-Injection Mode: In the “Checkbit-Injection” Mode, diagnostic checkbits may be input on System
Data Bus bits 0-7 (see Diagnostic Features - Detailed Description).
CLEAR: When the
Counter and the Error-Type Register are cleared.
SYNdrome CLocK: If
into the Syndrome Register and data from the outputs of the Memory Data input latch are clocked into the
Error-Data Register on the low-to-high edge of SYNCLK. If
the low-to-high edge of SYNCLK, unless the Error Counter indicates fifteen errors.
SynCLK ENable: The
CheckBits-Out (00, 01)
In a single EDC system, the checkbits are output to the checkbit memory on these outputs. In the lower slice
in a cascaded EDC system, the “Partial-checkbits” used by the upper slice are output by these outputs
(Generate path only). In the upper slice in a cascade, the “Final-Checkbits” appear at these outputs
(Generate path only).
CheckBits Out Enable: Enables CheckBit Output drivers when low.
SYndrome-Out (00)
In a 32-bit EDC system, the syndrome bits are output on these pins. In the lower slice in a 64-bit cascaded
system, the “Partial-Syndrome” bits appear at these outputs (Detect/ Correct path). In the upper slice in a
cascaded EDC system, the “Partial-Checkbits” appear at these outputs (Correct path only). In a 64-bit
cascaded system, the “Final-Syndrome” may be accessed in the “Diagnostic-Output” Mode from either the
lower or the upper slice since the final syndrome is contained in both.
ERROR: When in “Normal” and “Detect only” modes, a low on this pin indicates that one or more errors have
been detected.
+5 Volts
Ground
Multiple ERRor: When in “Normal” and “Detect only” modes, a low on this pin indicates that two or more
errors have been detected.
Parity ERRor: A low on this pin indicates a parity error which has resulted from the active bytes defined by
the 4 Byte Enable pins. Parity ERRor (
low. The Syndrome Register and Error-Data Register record the syndrome and uncorrected data
low. The Error Counter lets the system tell if more than one error has occurred since the last time
ERR
CLEAR
is not gated or latched internally.
ERR
SCLKEN
is low, and the Error Counter indicates zero errors, syndrome bits are clocked
MERR
pin is taken low, the Error-Data Register, the Syndrome Register, the Error
enables the SYNCLK signal. SYNCLK is ignored if
Partial-CheckBits-Out (10)
Partial-SYndrome-Out (10)
is not gated or latched internally.
11.7
PERR
Name and Function
) is not gated or latched internally (see Byte Enable definition).
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CLEAR
ERR
pin. The Syndrome Register and Error-Data
is low, the Error Counter will increment on
Checkbits-Out (11):
Partial-Checkbits-Out (11):
SCLKEN
ERR
is high.
= low),
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