idt49c465apqfb Integrated Device Technology, idt49c465apqfb Datasheet - Page 31

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idt49c465apqfb

Manufacturer Part Number
idt49c465apqfb
Description
32-bit Flow-thru Error Detection Correction Unit
Manufacturer
Integrated Device Technology
Datasheet
IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
AC TIMING DIAGRAMS — 64-BIT CONFIGURATION
NOTE:
1. Assumes that System Data is valid at least 3ns (Com.)/4ns (Mil.) before SLE goes HIGH.
SD
MD
CBOE
PERR
PCBI
MOE
CBO
CBO
BOTH
SOE
(L & U)
(L & U)
BE
SLE
465s
P
N
x
LOWER 465
UPPER 465
(OUTPUT)
(INPUT)
to
to
t SLM
t MEMZx
t BEM
t SESxZ
t CECZx
(1)
t SESxZ
1
1
t SSLS
t SLC
Figure 10. 64-Bit Generate Timing — (64-Bit Cascading System)
t SM
DATA
Parity In
(1)
2
2
t SSLH
t SC
t PPE
IN
MD DATA
3
3
3
Partial Checkbits Out
t PCC
Partial Checkbits In
OUT
=
Final Checkbits Out
4
4
SD DATA
11.7
IN
5
5
Parameter
t SESxZ min.
t SESxZ max.
Inter-chip delay (Design dependent)
t SLM
t SSLS
t SSLH
t PPE
t SM
t MEMZx
t BEM
t SC
t SLC
t CECZx
t PCC
Name
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(1)
(1)
SLE = High to MD
SOE = High to SD
SOE = High to SD
SD
SD
Px to PERR
SD
MOE = Low to MD
BE
SD Lower In to CBO
SLE
CBOE = Low to CBO Enabled
PCBI to CBO
From
N
IN
IN
IN
Propagation Delay
IN
to MD
Set-up to SLE
Hold to SLE
to MD
= High to CBO
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
= Low
= Low
(1)
Disabled
Disabled
Enabled
To
2552 drw 22
Min./
Max.
max.
min.
max.
min.
min.
max.
max.
max.
max.
max.
max.
max.
max.
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