idt49c465apqfb Integrated Device Technology, idt49c465apqfb Datasheet - Page 33

• Manufacturer Part Number: idt49c465apqfb
• Description: 32-bit Flow-thru Error Detection Correction Unit
• Manufacturer: Integrated Device Technology

IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
AC TIMING DIAGRAMS — 64-BIT CONFIGURATION
NOTE:
1. Assumes that Memory Data and Checkbits are valid at least 4ns (Com.) before MLE goes HIGH.
SD
MD
PCBI
U/L Slice
MOE
SOE
SYO
MLE
PLE
P
0–31
CBI
BE
64-BIT
0–31
0–3
N
(OUTPUT)
to
to
t BESZx
t SESZx
t MEMxZ
1
1
t BEPZx
t SEP
Valid Checkbits In
t MMLS
Valid DATA
t CMLS
t MLS
t PLS
t MLP
t PLP
t MSY
t CSY
t CSY
t MS
t MP
t CS
(1)
(1)
t MMLH
2
t CMLH
2
IN
Figure 12. 64-Bit Correct Timing (Lower Slice)
Partial checkbits in from Upper
3
3
Corrected DATA
Parity Out
Partial Syndrome Out
4
4
11.7
OUT
5
5
Parameter
t MEMxZ
t MMLS
t MMLH
t CMLS
t CMLH
t MLS
t PLS
t BESZx
t SESZx
t CS
t CSY
t MS
t CSY
t MSY
t MP
t MLP
t PLP
t BEPZx
t SEP
Name
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(1)
(1)
MOE = High to MD
MD
MD
CBI Set-up to MLE = Low
CBI Hold to MLE = Low
MLE
PLE = Low to SD
BE
SOE = Low to SD
CBI to Corrected SD
CBI to Syndrome
MD
CBI to Syndrome
MD
MD
MLE = High to Parity Out
PLE = Low to Parity Out
BE
SOE = Low to Parity Out
From
N
N
IN
IN
IN
IN
IN
IN
= High to SD
= High to Parity Out
Set-up to MLE = Low
Hold to MLE = Low
to Corrected SD
to Syndrome
to Parity Out
Propagation Delay
= High to SD
OUT
OUT
OUT
OUT
OUT
OUT
(1)
Enabled
OUT
Enabled
Disabled
(1)
To
2552 drw 24
Min./
Max.
max.
min.
min.
min.
min.
max.
max.
max.
max.
max.
max.
max.
max.
max.
max.
max.
max.
max.
max.
33