pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 87

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
14.1.36
14.1.37
14.1.38
UPSTREAM (S TO P) MEMORY BASE UPPER 32-BITS REGISTER
– OFFSET 54h
UPSTREAM (S TO P) MEMORY LIMIT UPPER 32-BITS
REGISTER – OFFSET 58h
P_SERR_L EVENT DISABLE REGISTER – OFFSET 64h
Bit
31:0
Bit
31:0
Bit
0
1
2
3
4
Function
Upstream
Memory Base
Address
Function
Upstream
Memory Limit
Address
Function
Reserved
Posted Write
Parity Error
Posted Write
Non-Delivery
Target Abort
During Posted
Write
Master Abort On
Posted Write
Type
R/W
Type
R/W
Type
R/O
R/W
R/W
R/W
R/W
Page 87 of 108
Description
Defines bits [63:32] of the upstream memory base
Reset to 0
Description
Defines bits [63:32] of the upstream memory limit
Reset to 0
Description
Reserved. Returns 0 when read. Reset to 0
Controls PI7C8150B’s ability to assert P_SERR_L when it is unable
to transfer any read data from the target after 2
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set.
1: P_SERR_L is not assert if this event occurs.
Reset to 0
Controls PI7C8150B’s ability to assert P_SERR_L when it is unable
to transfer delayed write data after 2
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
Controls PI7C8150B’s ability to assert P_SERR_L when it receives a
target abort when attempting to deliver posted write data.
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
Controls PI7C8150B’s ability to assert P_SERR_L when it receives a
master abort when attempting to deliver posted write data.
0: P_SERR# is asserted if this event occurs and the SERR# enable bit
in the command register is set
1: P_SERR# is not asserted if this event occurs
Reset to 0
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
24
attempts.
24
attempts.
PI7C8150B