pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 70

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
11
12
12.1
Table 11-1. Power Management Transitions
PCI POWER MANAGEMENT
PI7C8150B incorporates functionality that meets the requirements of the PCI Power
Management Specification, Revision 1.0. These features include:
Table 11-1 shows the states and related actions that PI7C8150B performs during power
management transitions. (No other transactions are permitted.)
PME# signals are routed from downstream devices around PCI-to-PCI bridges. PME#
signals do not pass through PCI-to-PCI bridges.
RESET
This chapter describes the primary interface, secondary interface, and chip reset
mechanisms.
PRIMARY INTERFACE RESET
PI7C8150B has a reset input, P_RESET_L. When P_RESET_L is asserted, the following
events occur:
D0
D0
D0
D0
D3hot
D3hot
D3cold
Current Status
PCI Power Management registers using the Enhanced Capabilities Port (ECP) address
mechanism
Support for D0, D3
Support for D0, D1, D2, D3
behind the bridge
Support of the B2 secondary bus power state when in the D3
state
PI7C8150B immediately tri-states all primary and secondary PCI interface signals.
D3cold
D3hot
D2
D1
D0
D3cold
D0
Next State
hot
and D3
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hot
cold
Power has been removed from PI7C8150B. A power-up reset must
be performed to bring PI7C8150B to D0.
If enabled to do so by the BPCCE pin, PI7C8150B will disable the
secondary clocks and drive them LOW.
Unimplemented power state. PI7C8150B will ignore the write to the
power state bits (power state remains at D0).
Unimplemented power state. PI7C8150B will ignore the write to the
power state bits (power state remains at D0).
PI7C8150B enables secondary clock outputs and performs an internal
chip reset. Signal S_RST_L will not be asserted. All registers will
be returned to the reset values and buffers will be cleared.
Power has been removed from PI7C8150B. A power-up reset must
be performed to bring PI7C8150B to D0.
Power-up reset. PI7C8150B performs the standard power-up reset
functions as described in Section 12.
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
, and D3
power management states
cold
power management states for devices
Action
APRIL 2006 – Revision 2.02
hot
power management
PI7C8150B