pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 27

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
3.5.6
3.6
3.6.1
3.6.2
FAST BACK-TO-BACK TRANSACTIONS
PI7C8150B can recognize and post fast back-to-back write transactions.
When PI7C8150B cannot accept the second transaction because of buffer
space limitations, it returns a target retry to the initiator. The fast back-to-back enable bit
must be set in the command register for upstream write transactions, and in the bridge
control register for downstream write transactions.
READ TRANSACTIONS
Delayed read forwarding is used for all read transactions crossing PI7C8150B. Delayed
read transactions are treated as either prefetchable or non-prefetchable. Table 3-5 shows the
read behavior, prefetchable or non-prefetchable, for each type of read operation.
PREFETCHABLE READ TRANSACTIONS
A prefetchable read transaction is a read transaction where PI7C8150B performs
speculative DWORD reads, transferring data from the target before it is requested from the
initiator. This behavior allows a prefetchable read transaction to consist of multiple data
transfers. However, byte enable bits cannot be forwarded for all data phases as is done for
the single data phase of the non-prefetchable read transaction. For prefetchable read
transactions, PI7C8150B forces all byte enable bits to be turned on for all data phases.
Prefetchable behavior is used for memory read line and memory read multiple transactions,
as well as for memory read transactions that fall into prefetchable memory space.
The amount of data that is pre-fetched depends on the type of transaction. The amount of
pre-fetching may also be affected by the amount of free buffer space available in
PI7C8150B, and by any read address boundaries encountered.
Pre-fetching should not be used for those read transactions that have side effects in the
target device, that is, control and status registers, FIFO’s, and so on. The target device’s
base address register or registers indicate if a memory address region is prefetchable.
NON-PREFETCHABLE READ TRANSACTIONS
A non-prefetchable read transaction is a read transaction where PI7C8150B requests one
and only one DWORD from the target and disconnects the initiator after delivery of the
first DWORD of read data. Unlike prefetchable read transactions, PI7C8150B forwards the
read byte enable information for the data phase.
Non-prefetchable behavior is used for I/O and configuration read transactions, as well as
for memory read transactions that fall into non-prefetchable memory space.
If extra read transactions could have side effects, for example, when accessing a FIFO, use
non-prefetchable read transactions to those locations. Accordingly, if it is important to
retain the value of the byte enable bits during the data phase, use non-prefetchable read
transactions. If these locations are mapped in memory space, use the memory read
command and map the target into non-prefetchable (memory-mapped I/O) memory space
to use non-prefetching behavior.
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
PI7C8150B