pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 84

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
14.1.30
ARBITER CONTROL REGISTER – OFFSET 40h
Bit
4
5
7:6
8
10:9
15:11
Bit
24:16
25
31:26
Function
Secondary Bus
Prefetch Disable
Live Insertion
Mode
Reserved
Chip Reset
Test Mode For
All Counters at P
and S1
Reserved
Function
Arbiter Control
Priority of
Secondary
Interface
Reserved
Type
R/W
R/W
R/O
R/WR
R/O
R/O
Type
R/W
R/W
R/O
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Description
Controls the bridge’s ability to prefetch during upstream memory
read transactions.
0: The bridge prefetches and does not forward byte enable bits during
upstream memory reads.
1: The bridge requests only 1 DWORD from the target and forwards
read byte enable bits during upstream memory reads.
Reset to 0
Enables hardware control of transaction forwarding.
0: GPIO[3] has no effect on the I/O, memory, and master enable bits
1: If GPIO[3] is set to input mode, this bit enables GPIO[3] to mask
I/O enable, memory enable and master enable bits to 0. PI7C8150B
will stop accepting I/O and memory transactions as a result.
Reset to 0
Reserved. Returns 0 when read. Reset to 0
Controls the chip and secondary bus reset.
0: PI7C8150B is ready for operation
1: Causes PI7C8150B to perform a chip reset
Controls the testability of the bridge’s internal counters.
The bits are used for chip test only.
00: all bits are exercised
01: byte 1 is exercised
10: byte 2 is exercised
11: byte 3 is exercised
Reset to 0
Reserved. Returns 0 when read. Reset to 0.
Description
Each bit controls whether a secondary bus master is assigned to the
high priority group or the low priority group.
Bits [24:16] correspond to request inputs S_REQ_L[8:0]
respectively.
Bit 24 corresponds to S_REQ_L[8]
Bit 16 corresponds to S_REQ_L[0]
0: low priority
1: high priority
Reset to 0
Controls whether the secondary interface of the bridge is in the high
priority group or the low priority group.
0: low priority
1: high priority
Reset to 1
Reserved. Returns 0 when read. Reset to 0.
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
PI7C8150B