pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 55

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
6.3
During upstream write transactions, when a data parity error is reported on the target
(primary) bus by the target’s assertion of P_PERR_L, the following events occur:
Assertion of P_SERR_L is used to signal the parity error condition when the initiator does
not know that the error occurred. Because the data has already been delivered with no
errors, there is no other way to signal this information back to the initiator. If the parity
error has forwarded from the initiating bus to the target bus, P_SERR_L will not be
asserted.
DATA PARITY ERROR REPORTING SUMMARY
In the previous sections, the responses of PI7C8150B to data parity errors are presented
according to the type of transaction in progress. This section organizes the responses of
PI7C8150B to data parity errors according to the status bits that PI7C8150B sets and the
signals that it asserts. Table 6-1 shows setting the detected parity error bit in the status
register, corresponding to the primary interface. This bit is set when PI7C8150B detects a
parity error on the primary interface.
PI7C8150B asserts P_SERR_L and sets the signaled system error bit in the status
register, if all the following conditions are met:
PI7C8150B sets the data parity detected bit in the status register, if the parity error
response bit is set in the command register of the primary interface.
PI7C8150B asserts P_SERR_L and sets the signaled system error bit in the status
register, if all the following conditions are met:
The SERR_L enable bit is set in the command register.
The posted write parity error bit of P_SERR_L event disable register is not
set.
The parity error response bit is set in the bridge control register of the
secondary interface.
The parity error response bit is set in the command register of the primary
interface.
PI7C8150B has not detected the parity error on the primary (initiator) bus
which the parity error is not forwarded from the primary bus to the
secondary bus.
The SERR_L enable bit is set in the command register.
The parity error response bit is set in the bridge control register of the
secondary interface.
The parity error response bit is set in the command register of the primary
interface.
PI7C8150B has not detected the parity error on the secondary (initiator)
bus, which the parity error is not forwarded from the secondary bus to the
primary bus.
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
PI7C8150B