pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 80

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
14.1.17
14.1.18
14.1.19
14.1.20
MEMORY BASE REGISTER – OFFSET 20h
MEMORY LIMIT REGISTER – OFFSET 20h
PEFETCHABLE MEMORY BASE REGISTER – OFFSET 24h
PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h
Bit
3:0
15:4
Bit
19:16
31:20
Bit
3:0
15:4
Bit
19:16
31:20
Function
Memory Base
Address [15:4]
Function
Memory Limit
Address [31:20]
Function
64-bit addressing
Prefetchable
Memory Base
Address [31:20]
Function
64-bit addressing
Prefetchable
Memory Limit
Address [31:20]
Type
R/O
R/W
Type
R/O
R/W
Type
R/O
R/W
Type
R/O
R/W
Page 80 of 108
Description
Indicates 64-bit addressing
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 1
Defines the bottom address of an address range for the bridge to
determine when to forward memory read and write transactions from
one interface to the other. The upper 12 bits correspond to address
bits [31:20] and are writable. The lower 20 bits are assumed to be 0.
Description
Indicates 64-bit addressing
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 1
Defines the top address of an address range for the bridge to
determine when to forward memory read and write transactions from
one interface to the other. The upper 12 bits correspond to address
bits [31:20] and are writable. The lower 20 bits are assumed to be
FFFFFh.
Description
Lower four bits of register are read only and return 0.
Reset to 0
Defines the bottom address of an address range for the bridge to
determine when to forward memory transactions from one interface
to the other. The upper 12 bits correspond to address bits [31:20]
and are writable. The lower 20 bits corresponding to address bits
[19:0] are assumed to be 0.
Reset to 0
Description
Lower four bits of register are read only and return 0.
Reset to 0
Defines the top address of an address range for the bridge to
determine when to forward memory transactions from one interface
to the other. The upper 12 bits correspond to address bits [31:20]
and are writable. The lower 20 bits corresponding to address bits
[19:0] are assumed to be FFFFFh.
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
PI7C8150B