pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 52

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
6.2.3
DELAYED WRITE TRANSACTIONS
When PI7C8150B detects a data parity error during a delayed write transaction, the
initiator drives data and data parity, and the target checks parity and conditionally asserts
PERR_L.
For delayed write transactions, a parity error can occur at the following times:
When a delayed write transaction is normally queued, the address, command, address
parity, data, byte enable bits, and data parity are all captured and a target retry is returned to
the initiator. When PI7C8150B detects a parity error on the write data for the initial
delayed write request transaction, the following events occur:
Note: If parity checking is turned off and data parity errors have occurred for queued or
subsequent delayed write transactions on the initiator bus, it is possible that the initiator’s
re-attempts of the write transaction may not match the original queued delayed write
information contained in the delayed transaction queue. In this case, a master timeout
condition may occur, possibly resulting in a system error (P_SERR_L assertion).
For downstream transactions, when PI7C8150B is delivering data to the target on the
secondary bus and S_PERR_L is asserted by the target, the following events occur:
Similarly, for upstream transactions, when PI7C8150B is delivering data to the target on
the primary bus and P_PERR_L is asserted by the target, the following events occur:
During the original delayed write request transaction
When the initiator repeats the delayed write request transaction
When PI7C8150B completes the delayed write transaction to the target
If the parity-error-response bit corresponding to the initiator bus is set, PI7C8150B
asserts TRDY_L to the initiator and the transaction is not queued. If multiple data
phases are requested, STOP_L is also asserted to cause a target disconnect. Two cycles
after the data transfer, PI7C8150B also asserts PERR_L.
If the parity-error-response bit is not set, PI7C8150B returns a target retry.
It queues the transaction as usual. PI7C8150B does not assert PERR_L.
In this case, the initiator repeats the transaction.
PI7C8150B sets the detected-parity-error bit in the status register corresponding to the
initiator bus, regardless of the state of the parity-error-response bit.
PI7C8150B sets the secondary interface data parity detected bit in the secondary status
register, if the secondary parity error response bit is set in the bridge control register.
PI7C8150B captures the parity error condition to forward it back to the initiator on the
primary bus.
PI7C8150B sets the primary interface data-parity-detected bit in the status register, if
the primary parity-error-response bit is set in the command register.
Page 52 of 108
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
PI7C8150B