pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 51

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
6.2.2
PI7C8150B sets the detected parity error bit in the status register, regardless of the state of
the parity error response bit.
READ TRANSACTIONS
When PI7C8150B detects a parity error during a read transaction, the target drives data and
data parity, and the initiator checks parity and conditionally asserts PERR_L. For
downstream transactions, when PI7C8150B detects a read data parity error on the
secondary bus, the following events occur:
For upstream transactions, when PI7C8150B detects a read data parity error on the primary
bus, the following events occur:
PI7C8150B returns to the initiator the data and parity that was received from the target.
When the initiator detects a parity error on this read data and is enabled to report it, the
initiator asserts PERR_L two cycles after the data transfer occurs. It is assumed that the
initiator takes responsibility for handling a parity error condition; therefore, when
PI7C8150B detects PERR_L asserted while returning read data to the initiator, PI7C8150B
does not take any further action and completes the transaction normally.
PI7C8150B asserts S_PERR_L two cycles following the data transfer, if the secondary
interface parity error response bit is set in the bridge control register.
PI7C8150B sets the detected parity error bit in the secondary status register.
PI7C8150B sets the data parity detected bit in the secondary status register, if the
secondary interface parity error response bit is set in the bridge control register.
PI7C8150B forwards the bad parity with the data back to the initiator on the primary
bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the
primary bus, the data is discarded and the data with bad parity is not returned to the
initiator.
PI7C8150B completes the transaction normally.
PI7C8150B asserts P_PERR_L two cycles following the data transfer, if the primary
interface parity error response bit is set in the command register.
PI7C8150B sets the detected parity error bit in the primary status register.
PI7C8150B sets the data parity detected bit in the primary status register, if the
primary interface parity-error-response bit is set in the command register.
PI7C8150B forwards the bad parity with the data back to the initiator on the secondary
bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the
secondary bus, the data is discarded and the data with bad parity is not returned to the
initiator.
PI7C8150B completes the transaction normally.
Page 51 of 108
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
PI7C8150B